3D NOR Array Vertical Stacks for High Density Memory
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Solution Overview
Problem
Existing NOR memory devices face challenges in achieving high access speed and density due to the limitations of two-dimensional memory cell structures.
Innovation Solution
The semiconductor structure comprises vertically-alternating stacks of insulating and conductive strips, laterally-alternating sequences of semiconductor channels and source/drain pillar structures, and memory films located between these stacks and sequences, enabling direct contact between source/drain pillar structures and vertical semiconductor channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If two-dimensional memory cell structures are used, then device complexity is reduced, but access speed and memory density are limited
Solution Approach 1:
The patent transitions from a two-dimensional memory cell structure to a three-dimensional structure by stacking multiple layers of memory cells vertically. Each layer includes alternating stacks of insulating and conductive strips with semiconductor channels extending vertically, enabling direct access to memory cells from the top surface without passing through adjacent cells, thereby achieving faster access speed while maintaining manageable device complexity through standardized layer repetition
Solution Approach 2:
The memory device is segmented into multiple functional layers including insulating strips, conductive strips, semiconductor channels, and memory films arranged in alternating stacks. Each layer performs a specific function (e.g., insulation, conduction, charge storage), allowing independent optimization of each segment while contributing to the overall high access speed and density of the three-dimensional structure
2Quantity of substance
If two-dimensional memory cell structures are used, then manufacturing process is simpler, but memory density is limited
Solution Approach 1:
The patent achieves high memory density by extending the memory cell structure into the third dimension through vertical stacking. Multiple layers of memory cells are stacked along the vertical direction, significantly increasing the quantity of memory cells per unit area. The repeating pattern of insulating and conductive strips with semiconductor channels creates a scalable three-dimensional architecture that maximizes memory density while using standardized manufacturing processes for each layer
Solution Approach 2:
The three-dimensional memory structure employs a nested arrangement where multiple functional components are integrated within each other. Semiconductor channels are surrounded by memory films, which are in turn surrounded by alternating insulating and conductive strips. This nested configuration allows maximum packing of memory elements within the available space, achieving high memory density without proportionally increasing manufacturing complexity
Data Source
AI summary
A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.