3D NOR Memory Cell Array Bonding for Low-Resistance Scaling
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Solution Overview
Problem
Vertical NOR-type memory devices face challenges in scaling down due to the use of polycrystalline silicon as a channel material, leading to increased resistance and poor performance, while stacking these devices for higher integration density results in suboptimal performance and bandwidth connections with peripheral circuits.
Innovation Solution
A NOR-type memory device is designed with a 3D structure using monocrystalline material as a constructing block, where the memory cell array is bonded with a peripheral circuit to enhance bandwidth connection, and a method of manufacturing involves forming a gate stack that extends vertically through multiple device layers, allowing for efficient stacking and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical devices are stacked to increase integration density, then integration density is improved, but resistance increases due to use of polycrystalline silicon as channel material
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to monocrystalline silicon for the channel material. This parameter change maintains the vertical stacking configuration for high integration density while significantly reducing channel resistance, as monocrystalline silicon has superior electrical properties compared to polycrystalline silicon.
2Quantity of substance
If vertical devices are stacked to increase integration density, then integration density is improved, but bandwidth connection between memory cells and peripheral circuit deteriorates
Solution Approach 1:
The patent transitions from a planar two-dimensional connection architecture to a three-dimensional vertical connection architecture. By stacking memory cell layers vertically and providing corresponding bonding pads on opposite surfaces of the substrate, the patent achieves high-bandwidth connections in the vertical dimension while maintaining high integration density through the same stacking approach.
3Ease of manufacture
If planar device arrangement is used, then ease of manufacture is maintained, but scaling down becomes difficult
Solution Approach 1:
The patent transitions from planar two-dimensional device arrangement to vertical three-dimensional device arrangement. By stacking multiple device layers vertically on the substrate, the patent achieves continuous scaling down of device dimensions while maintaining manufacturability through standard vertical stacking and bonding processes.
Data Source
AI summary
Disclosed are a NOR-type memory device and an electronic apparatus. The NOR-type memory device includes a NOR cell array and a peripheral circuit. The NOR cell array includes: a first substrate; an array of memory cells on the first substrate, wherein each memory cell includes a first gate stack extending vertically with respect to the first substrate and an active region surrounding a periphery of the first gate stack; first bonding pads electrically connected to the first gate stacks; and second bonding pads electrically connected to the active regions. The peripheral circuit includes: a second substrate; peripheral circuit elements on the second substrate; and third bonding pads, wherein at least some of the third bonding pads are electrically connected to the peripheral circuit elements. At least some of the first bonding pads and the second bonding pads are opposite to at least some of the third bonding pads.