3D NOR FeFET Memory Array Vertical Stacking Integration
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Solution Overview
Problem
Current semiconductor memory devices, particularly volatile memories like SRAM and DRAM, lose data when powered off, and non-volatile FeRAMs face challenges in scalability and integration efficiency in three-dimensional memory arrays.
Innovation Solution
A three-dimensional (3D) NOR-type memory array is developed using ferroelectric field effect transistors (FeFETs) with vertically stacked memory cells, incorporating a ferroelectric material as a gate dielectric and an oxide semiconductor channel region, and an oxide-nitride-oxide (ONO) stacked structure, enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked memory cells are implemented to improve integration efficiency, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangements to a three-dimensional vertically stacked configuration. Multiple memory cells are stacked along the vertical direction, with each cell comprising source/drain regions, channel regions, and gate electrodes at different height levels. This dimensional transition dramatically increases storage density per unit area while maintaining compatibility with standard semiconductor manufacturing processes through sequential deposition and patterning steps.
Solution Approach 2:
The memory device is segmented into multiple independently functional memory cells stacked vertically. Each memory cell operates as a discrete unit with its own source/drain regions, channel, and gate electrode. This segmentation allows for modular manufacturing where each cell layer can be processed and formed through systematic repetition of deposition, patterning, and etching cycles, making the complex 3D structure manufacturable through standardized process modules.
2Reliability
If ferroelectric material is used as gate dielectric to enable non-volatile storage, then data retention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies precise thickness parameters for the ferroelectric gate dielectric layer to ensure proper functionality. The ferroelectric layer thickness is controlled within specific ranges (e.g., 5-20 nm) to achieve the desired ferroelectric effect while maintaining compatibility with existing manufacturing capabilities. By optimizing and controlling this critical parameter, the patent achieves reliable non-volatile data retention without requiring breakthroughs in manufacturing precision beyond current industry standards.
Solution Approach 2:
The gate dielectric structure employs a composite configuration combining ferroelectric material with conventional dielectric materials in layered arrangements. This composite approach leverages the non-volatile properties of ferroelectric materials while using conventional dielectrics for electrical isolation and structural support, thereby achieving data retention improvements without excessively stringent manufacturing precision requirements for the ferroelectric layer alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D NOR-type memory array provides fast write/read speeds and compact design, addressing the data retention issues of volatile memories and enhancing integration efficiency in semiconductor devices.
Implementation Method 1
incorporating a ferroelectric material as a gate dielectric
Data Source
AI summary
A memory device including a word line, memory cells, source lines and bit lines is provided. The memory cells are embedded in and penetrate through the word line. The source lines and the bit lines are electrically connected the memory cells. A method for fabricating a memory device is also provided.