3D NOR Flash Memory Structure for High-Speed Dense Storage
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high read/write access speed and high density, with NAND-type flash memory being slow and NOR-type flash memory lacking in density, necessitating a new structure that combines high-speed access with high capacity.
Innovation Solution
A 3D semiconductor memory structure is developed, incorporating a NOR-type flash memory configuration with a 3D arrangement, featuring a stack of alternating insulating and semiconductor layers, trenches, charge-trapping layers, and conductive structures to enhance access speed and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND-type flash memory structure is used, then integration density is improved, but read/write access speed deteriorates
Solution Approach 1:
The patent transitions from traditional 2D planar memory structures to a 3D vertical stacking architecture. Multiple memory cell layers are stacked vertically, with each layer containing memory cells arranged in a NOR configuration. This dimensional change enables simultaneous achievement of high density through vertical integration and high speed through parallel access to multiple layers, resolving the contradiction between density and speed that plagues conventional NAND structures.
Solution Approach 2:
The memory device is divided into multiple stacked layers, each containing independently addressable memory cells. The word lines are segmented into multiple sets (first word lines, second word lines, etc.) that can be independently controlled. This segmentation allows parallel operation of multiple memory cell layers, achieving high-speed access while maintaining high integration density through vertical stacking.
2Speed
If NOR-type flash memory structure is used, then read/write access speed is improved, but integration density deteriorates
Solution Approach 1:
By stacking multiple NOR-type memory cell layers vertically in the third dimension, the patent achieves high integration density without sacrificing the high-speed access characteristics of NOR architecture. The vertical stacking multiplies the storage capacity while maintaining parallel read/write capabilities across all layers, thus resolving the density limitation of conventional NOR flash memory.
3Quantity of substance
If critical dimensions are scaled down, then integration density is improved, but manufacturing precision requirements worsen
Solution Approach 1:
Instead of continuing to scale down critical dimensions in the lateral direction, which demands ever-increasing manufacturing precision, the patent scales vertically by stacking multiple memory cell layers. This approach achieves higher integration density by utilizing the third dimension, thereby avoiding the exponential increase in manufacturing precision requirements that would result from further lateral scaling.
Data Source
AI summary
A semiconductor memory structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked over a substrate, and at least an active column disposed over the substrate. The gate layers and the insulating layers are alternately stacked along a first direction. The active column extends along the first direction and penetrates the gate layer and the insulating layer. The active column includes a central portion, a charge-trapping layer surrounding the central portion, and a channel layer between the central portion and the charge-trapping layer. The central portion of the active column includes an isolation structure, a source structure and a drain structure. The source structure and the drain structure are disposed at two sides of the isolation structure.