3D Vertical NOR Flash Strings for Faster Read Current
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Solution Overview
Problem
Conventional three-dimensional NAND memory structures suffer from low read current due to low conductivity of thin film transistors, leading to slow read access and susceptibility to read-disturb and program-disturb conditions, while conventional NOR structures face limitations in parallel programming efficiency and susceptibility to program-disturb conditions.
Innovation Solution
The development of three-dimensional vertical NOR flash memory strings with parallel-connected thin film transistors, featuring a shared source and drain region, and multiple horizontal control gates, allowing independent activation of each transistor for reading or programming, and incorporating charge-trapping materials for efficient programming and reduced disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional vertical NAND memory structures are used, then memory density is improved, but read current is reduced leading to slow read access
Solution Approach 1:
The patent inverts the conventional NAND string architecture by switching from series-connected transistors to parallel-connected transistors. This fundamental inversion changes the current flow characteristics, enabling high read current while maintaining high density through the three-dimensional vertical structure. The parallel connection allows multiple transistors to contribute to read current simultaneously, resolving the contradiction between density and read speed.
Solution Approach 2:
The patent changes the connectivity parameter from series to parallel, fundamentally altering the electrical characteristics of the memory string. This parameter change enables the memory structure to achieve both high density (through vertical stacking) and high read current (through parallel transistor connections), directly resolving the technical contradiction.
2Speed
If conventional NOR structures are used, then read access speed is improved, but parallel programming efficiency is reduced
Solution Approach 1:
The patent segments the programming operation into independent transistor-level operations. Each transistor in the parallel-connected string can be programmed independently through its own control gate, enabling massive parallel programming efficiency. This segmentation approach maintains the fast read access characteristic of NOR structures while dramatically improving programming throughput.
Solution Approach 2:
The patent enables programming of individual transistors within the string rather than requiring all transistors to be programmed simultaneously. This partial action capability allows flexible programming operations where only selected transistors need to be programmed, significantly improving parallel programming efficiency while maintaining fast read access.
3Ease of manufacture
If thin film transistors with low conductivity are used, then manufacturing is simplified, but read current is reduced
Solution Approach 1:
The patent merges multiple low-conductivity transistors in parallel to achieve high total read current. While individual thin film transistors have low conductivity, the parallel combination of many such transistors produces sufficient read current. This merging approach maintains the manufacturing simplicity of thin film transistors while overcoming their low conductivity limitation.
Data Source
AI summary
A memory structure including a storage transistor having a data storage storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor being configurable to have a threshold voltage that is representative of data stored in the data storage region; a word line electrically connected to the gate terminal, configured to provide a control voltage during a read operation; a bit line electrically connecting the first drain or source terminal to data detection circuitry; and a source line electrically connected to the second drain or source terminal, configured to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.