3D Vertical NOR Flash Strings for Faster Low-Disturb Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional three-dimensional vertical NAND strings suffer from high read latency and are susceptible to read-disturb and program-disturb conditions due to their series-connected transistors, which limits the number of transistors that can be included and results in lower read current compared to NOR strings.
Innovation Solution
The implementation of three-dimensional vertical NOR Flash memory strings with multiple thin-film transistors connected in parallel, sharing a common source and drain region, and controlled by multiple horizontal control gates, allowing for faster read and programming operations by activating only the necessary transistor while keeping others dormant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are connected in series (NAND string configuration), then storage density is improved, but read latency increases and read current decreases
Solution Approach 1:
The invention divides the memory string into multiple parallel transistor segments (TFT1, TFT2, TFT3, etc.) that can be independently controlled by separate control gates (CG1, CG2, CG3, etc.). This segmentation allows selective activation of only the necessary transistor segment for reading, eliminating the need to activate all series-connected transistors and thereby reducing read latency while maintaining high storage density.
Solution Approach 2:
The invention transitions from a one-dimensional series connection (NAND) to a multi-dimensional parallel architecture where transistor segments are arranged both vertically and horizontally. Multiple control gates are positioned at different heights and angles, creating a three-dimensional control structure that enables independent access to different transistor segments, thus improving read speed without sacrificing density.
2Quantity of substance
If more transistors are included in the string, then storage density is improved, but susceptibility to read-disturb and program-disturb conditions increases
Solution Approach 1:
By segmenting the memory string into independently controllable transistor groups, the invention isolates disturb effects to specific segments. When reading or programming one segment, only the corresponding control gate is activated, preventing voltage disturbances from propagating to other segments. This maintains high storage density while improving reliability by containing disturb effects locally.
Solution Approach 2:
The control gates serve as intermediaries between the read/program circuits and the transistor segments. By using multiple control gates as mediators, the invention enables selective isolation of active segments from inactive ones, preventing harmful voltage effects from affecting transistors that are not currently being accessed, thus reducing read-disturb and program-disturb conditions.
3Speed
If transistors are connected in parallel (NOR string configuration), then read current and speed are improved, but the number of transistors per string is limited
Solution Approach 1:
The invention creates a multi-dimensional transistor array where parallel-connected transistor segments are arranged in multiple vertical and horizontal layers. By adding spatial dimensions to the parallel architecture, the system can accommodate many more transistors than a simple planar parallel configuration, thereby increasing storage density while maintaining the high read current and speed characteristics of parallel connections.
4Quantity of substance
If series-connected transistors are used, then storage density is improved, but read current decreases compared to NOR strings
Solution Approach 1:
The invention segments the high-density series-connected memory string into multiple parallel transistor groups, each with its own control gate. This allows the system to maintain the high storage density of series connections while enabling parallel access paths. When reading, only one segment needs to be activated, providing sufficient read current without requiring all transistors to be conductive, thus resolving the conflict between density and read current.
Data Source
AI summary
A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.