3D NOR Flash Memory Staircase Gate Structure
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Solution Overview
Problem
Conventional 2D flash memory devices face scaling limitations, necessitating the development of 3D architectures to enhance the scalability of read operations and data capacity for NOR flash memory devices.
Innovation Solution
A three-dimensional memory cell structure is introduced, comprising a staircase configuration formed by conductive layers, dielectric layers, and a channel conductive layer, which improves gate capacity and reduces current leakage in 3D NOR flash memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D flash memory architecture is used, then manufacturing process is simpler, but scaling limitations occur and data capacity is restricted
Solution Approach 1:
The patent transitions from conventional 2D flash memory architecture to a 3D architecture by stacking multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) vertically. This dimensional change enables increased data capacity by utilizing the third dimension (depth) for additional memory cells, thereby resolving the scaling limitations of 2D architectures while maintaining manufacturability through established layering techniques.
2Productivity
If 3D architecture is implemented to increase data capacity, then scalability of read operations is improved, but current leakage increases
Solution Approach 1:
The patent segments the gate structure into multiple distinct conductive layers (first conductive layer for control gate, second conductive layer for floating gate, third conductive layer for additional control) separated by dielectric layers. This segmentation allows independent optimization of each layer's function, enabling improved read operation scalability while reducing current leakage through better electrical isolation between layers.
Solution Approach 2:
The patent introduces dielectric layers as intermediary materials between the conductive layers. These dielectric layers serve as electrical insulators that prevent current leakage between adjacent conductive layers while still allowing capacitive coupling for read operations, thereby enabling scalability without sacrificing electrical isolation.
3Quantity of substance
If dual-gate structure is used in conventional cells, then basic memory function is achieved, but gate capacity is insufficient for high-density 3D structures
Solution Approach 1:
The patent merges multiple gate functions into a unified multi-layer conductive structure where the first conductive layer (control gate), second conductive layer (floating gate), and third conductive layer (additional control gate) work together as an integrated system. This merging approach increases total gate capacity for high-density 3D structures while managing complexity through functional integration rather than separate discrete components.
Data Source
AI summary
Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.