3D NOR Flash Staircase Stack Layout for Lower Defect Manufacturing
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Solution Overview
Problem
Manufacturing 3D semiconductor memory devices with a complex circuit structure is challenging due to defects such as word line opens and pattern failures, making it difficult to achieve high memory capacity with a small area footprint.
Innovation Solution
A 3D semiconductor device with a staircase configuration of stack units, where conductive films and dielectric films are alternately stacked, and conductive pillars are used to form thin film transistors, allowing for a 3D NOR flash architecture with reduced defects through a staircase-first or staircase-last process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D architecture is used to increase memory capacity, then memory capacity is improved, but manufacturing complexity and defect rate increase
Solution Approach 1:
The 3D memory structure is divided into multiple stack units, each containing alternating dielectric layers and conductive layers. This segmentation allows for modular manufacturing and reduces the complexity of forming the entire 3D structure in one process, thereby reducing defects while maintaining high memory capacity.
Solution Approach 2:
Sacrificial layers are formed preliminarily between the dielectric layers during stack unit formation. These sacrificial layers facilitate subsequent etching processes to create conductive pillars and word lines, enabling precise 3D pattern formation and reducing manufacturing defects.
2Quantity of substance
If a 3D architecture is used to increase memory capacity, then memory capacity is improved, but circuit complexity increases
Solution Approach 1:
The patent transitions from 2D to 3D architecture by stacking multiple dielectric and conductive layers vertically to form stack units with conductive pillars extending through them. This dimensional change increases memory capacity without proportionally increasing circuit complexity, as the 3D structure enables more efficient space utilization and cell density.
3Ease of manufacture
If conventional manufacturing processes are used for 3D structures, then manufacturing is simpler, but defect rate increases due to difficult etching
Solution Approach 1:
Sacrificial layers are formed preliminarily between the dielectric layers during stack unit formation. These sacrificial layers facilitate subsequent etching processes to create conductive pillars and word lines, enabling precise 3D pattern formation and reducing manufacturing defects.
Solution Approach 2:
Sacrificial layers act as intermediary materials that enable the formation of complex 3D structures. These temporary structures guide the etching process and are later removed, allowing for precise pattern formation without directly increasing manufacturing complexity.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, first and second stack units disposed over the semiconductor substrate, and a feature disposed between the first and second stack units. Each of the first and second stack units includes at least one stack that includes a conductive film and a dielectric film stacked on each other. The feature includes a plurality of repeating units and a plurality of separators disposed to alternate with the repeating units. Each of the repeating units includes an inner portion including a pair of conductive pillars, and an outer portion including a memory film and a channel film. A method for manufacturing the semiconductor device is also disclosed.