3D NOR Memory Strings With Air-Gap Isolation for Fast Random Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory structures face challenges in achieving high-density, low read-latency, and randomly accessible memory solutions with efficient fabrication processes, particularly in three-dimensional arrays of NOR memory strings.
Innovation Solution
The development of a three-dimensional memory structure using NOR memory strings with a common source and drain layer configuration, isolated by sacrificial layers and conductive layers, and utilizing ferroelectric or charge-trap storage transistors with air gap isolation to reduce parasitic capacitance and enhance isolation between memory strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory structures are used, then manufacturing process is simpler, but memory density and read latency performance are insufficient
Solution Approach 1:
The patent transitions from planar two-dimensional memory architecture to three-dimensional vertical architecture by stacking multiple active layers (first active layer, second active layer, third active layer) vertically above the substrate. This dimensional change enables higher memory density by utilizing the vertical space dimension, allowing multiple memory strings to be stacked while maintaining individual addressability through word line control across different layers.
Solution Approach 2:
The memory structure is segmented into multiple independent active layers, each containing complete memory strings with source lines, bit lines, and gate electrodes. Each layer can be independently addressed and controlled, allowing parallel operation of multiple layers. This segmentation enables high-density storage while maintaining simplicity in fabrication processes through modular layer-by-layer construction.
2Productivity
If memory strings are closely packed to increase density, then memory density improves, but parasitic capacitance between adjacent strings increases
Solution Approach 1:
The patent introduces air gap isolation regions as intermediary spaces between adjacent memory strings and between different active layers. These air gaps act as electrical insulators with minimal parasitic capacitance, allowing memory strings to be closely packed for high density while maintaining electrical isolation. The air gaps are formed by removing sacrificial layers, creating void spaces that provide excellent isolation properties.
Solution Approach 2:
The memory structure utilizes air gaps (porous spaces) as isolation media between memory strings and layers. These void spaces provide electrical isolation with minimal dielectric constant, reducing parasitic capacitance effects. The porous air gap structure allows for high-density packing while maintaining low inter-string capacitance, improving read latency and signal integrity.
3Adaptability or versatility
If conventional fabrication processes are used, then manufacturing is easier, but integration with digital and analog circuits requires higher temperatures and voltages
Solution Approach 1:
The patent employs low-temperature fabrication parameters throughout the manufacturing process, including low-temperature deposition, annealing, and doping steps. This enables integration with sensitive digital and analog circuits that cannot withstand high temperatures. The process parameters are specifically optimized to remain below typical circuit damage thresholds, allowing monolithic integration of memory with logic and analog blocks on the same substrate.
Solution Approach 2:
The patent replaces conventional high-temperature thermal diffusion processes with low-temperature alternative methods such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and ion implantation at reduced energies. These substitutions enable fabrication at temperatures compatible with standard CMOS circuits, allowing seamless integration without requiring separate high-temperature processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density, low-cost memory arrays with low read latency and high endurance, supporting fast and random access operations, while allowing for integration with digital and analog circuits at lower temperatures and voltages.
Implementation Method 1
isolated by sacrificial layers and conductive layers, and utilizing ferroelectric or charge-trap storage transistors with air gap isolation to reduce parasitic capacitance
Implementation Method 2
By controlling the polarization direction in a ferroelectric gate dielectric layer, the FeFET may be programmed to have either one of two threshold voltages
Implementation Method 3
An applied electrical field across the charge storage film adds or removes charge from charge traps in the charge trapping layer, altering the threshold voltage of the storage transistor
Data Source
AI summary
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The storage transistors can be charge-trapping type storage transistors or ferroelectric storage transistors. The three-dimensional memory stacks are manufactured in a process that uses a sacrificial layer and access shafts to perform channel separation through a backside selective etch process. In some embodiments, the memory structure includes first and second semiconductor layers and respective first and second conductive layers forming the source and drain regions, which are spaced apart by a channel spacer dielectric layer. Each conductive layer is formed between the respective semiconductor layer and the channel spacer dielectric layer.