3D NOR Memory Array Structure for High-Density Low-Disturb Operation
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing integration density and reducing feature sizes in semiconductor devices, particularly in forming efficient 3D memory arrays with high production yield and minimal disturbances in read/write operations.
Innovation Solution
A 3D NOR memory array is formed using a multi-layer stack with alternating isolation and dummy layers, where gate trenches are etched, and semiconductor and memory films are deposited, followed by the formation of conductive structures and staircase contact structures to enhance connectivity and reduce material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lithography and sequential layer deposition are used to increase integration density, then more components can be integrated into a given area, but manufacturing complexity and production costs increase
Solution Approach 1:
The patent segments the manufacturing process into distinct modules: forming multi-layer stacks with alternating isolation and dummy layers, etching gate trenches, depositing semiconductor and memory films, and forming conductive structures. Each module can be independently optimized and controlled, reducing overall manufacturing complexity while achieving high integration density through systematic decomposition of the fabrication process.
Solution Approach 2:
The patent transitions from planar 2D memory structures to three-dimensional vertically stacked memory arrays. By stacking multiple memory cells vertically along the z-axis, the integration density is dramatically increased without proportionally increasing the lithographic feature size requirements, thereby improving productivity without exponentially increasing manufacturing complexity.
2Productivity
If 3D memory arrays are formed with complex multi-layer stacks, then integration density increases, but manufacturing yield decreases due to process variability
Solution Approach 1:
The patent forms complete multi-layer stacks with alternating isolation and dummy layers before etching gate trenches and depositing active materials. This preliminary structuring establishes a robust framework that guides subsequent processing steps, ensuring consistent alignment and reducing process variability. The pre-formed stacks act as self-aligned masks and structural guides, improving manufacturing yield despite the complexity of the final 3D structure.
Solution Approach 2:
The isolation layers and dummy layers serve as intermediary structures that mediate between the substrate and the active memory components. These intermediary layers provide mechanical support, thermal management, and process control during fabrication, reducing the impact of process variability on final device performance and improving production yield.
3Productivity
If feature sizes are reduced to increase integration density, then more memory cells fit in a given area, but read/write operations become more susceptible to disturbances
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent achieves high integration density without continuously reducing lateral feature sizes. The vertical stacking allows memory cells to be arranged in multiple layers (e.g., 32 layers) with sufficient spacing between layers, maintaining adequate signal integrity and reducing cross-talk disturbances while achieving high density through the third dimension rather than aggressive lateral scaling.
Solution Approach 2:
The patent segments the memory array into multiple vertically stacked layers with isolation layers between them. This segmentation physically separates adjacent memory cells both laterally and vertically, reducing electromagnetic interference and disturbance between neighboring cells. The segmented structure allows each memory cell to operate with sufficient isolation, minimizing read/write disturbances even as integration density increases through vertical stacking.
Data Source
AI summary
3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.