3D NOR Memory Cell Structure for Higher Integration Density
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Solution Overview
Problem
Current NOR memory devices face challenges in increasing integration density due to their two-dimensional structure, limiting further size reduction and capacity enhancement.
Innovation Solution
A novel NOR memory device structure is proposed, featuring vertically stacked source/drain contact layers and isolation layers, with a gate structure extending through them, allowing for three-dimensional stacking and improved integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells are connected in parallel (NOR structure), then read speed and random access capability are improved, but integration density deteriorates compared to series-connected NAND memory
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking by extending the gate structure vertically through multiple alternating layers of source/drain contact layers and isolation layers. This vertical dimension enables multiple memory cells to be stacked above each other, significantly increasing integration density while maintaining the parallel connection topology of NOR memory cells.
Solution Approach 2:
The patent implements nested structures where gate structures are vertically embedded through alternating source/drain contact layers and isolation layers. The semiconductor layer is positioned on the periphery of the gate structure, creating a nested arrangement where components are integrated within each other's spatial envelope, maximizing space utilization.
2Ease of manufacture
If traditional two-dimensional NOR memory structure is used, then manufacturing simplicity is maintained, but area occupation per memory cell increases
Solution Approach 1:
The patent reduces the area occupied by each memory cell by stacking multiple memory cells vertically in the third dimension. The alternating layers of source/drain contact layers and isolation layers are stacked vertically with gate structures extending through them, enabling multiple cells to share the same footprint area, thereby dramatically reducing the area per memory cell while maintaining manufacturing feasibility through extended vertical processing.
3Quantity of substance
If vertical stacking of source/drain contact layers and isolation layers is implemented, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory device into repeating units consisting of alternating source/drain contact layers and isolation layers stacked vertically. Each segment contains a gate structure extending through the layers and a semiconductor layer on its periphery, forming modular memory cells. This segmentation into standardized vertical units simplifies the overall device architecture despite the increased vertical complexity, as each segment follows the same structural pattern.
Data Source
AI summary
Disclosed is NOR memory device. The NOR memory device comprises: at least two source/drain contact layers and at least one isolation layer alternately stacked in a vertical direction; a gate structure vertically extending through the source/drain contact layers and the isolation layer; and a semiconductor layer on the periphery of the gate structure; wherein, two of the source/drain contact layers located immediately above and below the isolation layer are respectively connected to two bit/source lines, and form a memory transistor together with the gate structure and the semiconductor layer.