3D NOR Memory Strings for Fast Read and Lower Power
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Solution Overview
Problem
Existing high-density memory structures, such as NAND and NOR strings, face challenges with read-latency, program-disturb, and power dissipation, particularly in three-dimensional arrays, where NAND strings have high series resistance limiting the number of transistors and NOR strings require large electron currents for programming, leading to inefficiencies.
Innovation Solution
The implementation of NOR memory strings with horizontal active strips and vertical local word lines, where TFTs are organized in parallel, allowing for reduced read-latency, decreased power dissipation, and increased storage density by using quasi-volatile charge-storing elements with modified charge-storing structures for enhanced write/erase cycle endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND strings are used in three-dimensional arrays, then storage density is increased, but read-latency increases and program-disturb occurs due to high series resistance limiting the number of transistors
Solution Approach 1:
The patent inverts the traditional NAND string architecture by using NOR string configuration where memory cells are connected in parallel between bit lines and source lines, rather than in series. This inversion allows individual cell access without activating entire strings, reducing read-latency while maintaining high storage density through three-dimensional stacking of active strips
Solution Approach 2:
The patent transitions from planar two-dimensional memory organization to three-dimensional structures by stacking multiple active strips vertically with interspersed control gates. This dimensional change enables significantly increased storage density while the NOR string configuration within each strip maintains fast read access by avoiding series resistance issues
2Loss of time
If NOR strings are used, then read-latency is reduced, but power dissipation increases due to large electron currents required for programming
Solution Approach 1:
The patent applies local quality by using quasi-volatile charge-storing elements with modified structures in specific regions of the NOR strings. These modified charge-storing structures are localized at strategic positions to enhance write/erase cycle endurance and reduce the electron currents needed for programming, thereby reducing power dissipation while maintaining fast read-latency characteristics
Solution Approach 2:
The patent changes the parameters of charge-storing elements by using quasi-volatile structures with modified properties. These parameter changes in the charge-storing elements enable more efficient charge injection and retention, reducing the programming currents required and thus lowering power dissipation while preserving the fast read access of NOR architecture
3Ease of manufacture
If traditional charge-storing structures are used, then manufacturing is simpler, but write/erase cycle endurance is limited
Solution Approach 1:
The patent employs composite charge-storing structures combining multiple materials and layers with distinct functions. These composite structures integrate charge-trapping regions, tunnel dielectrics, and blocking dielectrics in specific configurations that enhance write/erase cycle endurance while remaining compatible with existing thin-film transistor fabrication processes, thus maintaining manufacturing simplicity
Data Source
AI summary
A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.