3D NOR Memory Device Inversion for Speed and Density
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Solution Overview
Problem
Three-dimensional NAND strings suffer from slower operational speed due to inherent delays during programming and sensing, limiting their performance in memory devices.
Innovation Solution
A NOR-type three-dimensional memory device is developed with a vertically alternating stack of insulating and conductive layers, featuring laterally alternating active region pillars and memory stack structures that are electrically isolated, allowing direct connection to source and drain regions without intermediate connections, enhancing operational speed and bit line density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional NAND strings are used to provide high density memory, then storage density is improved, but operational speed deteriorates due to inherent delays during programming and sensing
Solution Approach 1:
The patent inverts the conventional NAND string architecture by implementing a NOR-type memory device where memory cells are connected directly to source and drain regions in parallel, rather than in series. This inversion eliminates the inherent delays present in NAND strings during programming and sensing operations, thereby improving operational speed while maintaining high storage density through the three-dimensional vertically alternating stack structure
Solution Approach 2:
The patent transitions from planar or simple vertical structures to a complex three-dimensional architecture with vertically alternating insulating and conductive layers, combined with laterally alternating active region pillars and memory stack structures. This multi-dimensional arrangement enables direct connections to source and drain regions while maintaining high bit line density, resolving the contradiction between storage density and operational speed
2Quantity of substance
If vertically alternating stack structures are implemented to increase bit line density, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory device into distinct vertically alternating insulating layers and conductive layers, with laterally alternating active region pillars and memory stack structures. Each segment performs a specific function: insulating layers provide electrical isolation, conductive layers form bit lines, active region pillars serve as source/drain regions, and memory stack structures contain the memory cells. This segmentation enables high bit line density while managing complexity through modular functional division
Solution Approach 2:
The vertically alternating stack structure serves multiple functions simultaneously: it provides electrical isolation between bit lines, forms the bit lines themselves through conductive layers, supports memory cells in stack structures, and enables direct connections to source and drain regions. This multi-functionality increases bit line density without proportionally increasing device complexity
Data Source
AI summary
A NOR-type three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a substrate, and laterally alternating sequences of respective active region pillars and respective memory stack structures. Each laterally alternating sequence is electrically isolated from the electrically conductive layers by a respective blocking dielectric layer at each level of the electrically conductive layers. Each memory stack structures include a memory film and a semiconductor channel material portion that vertically extend through the vertically alternating stack. The active region pillars include an alternating sequence of source pillar and drain pillars.