3D NOR Memory Array With Vertical Word Lines and Self-Aligned Isolation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high access speed and efficient memory operations, particularly in NOR arrays, due to limitations in the design of memory cells and the integration of vertical word lines and ferroelectric memory elements.
Innovation Solution
A three-dimensional memory device is designed with an alternating stack of source and drain layers over a substrate, featuring vertical word lines and discrete semiconductor channels, along with memory material portions laterally surrounding the word lines, formed through a method involving unit layer stacks, memory openings, and sacrificial spacer layers to enable efficient memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells are connected in parallel with direct source and drain connections (NOR configuration), then access speed is improved, but device complexity increases when integrating vertical word lines and ferroelectric memory elements in three-dimensional structure
Solution Approach 1:
The memory device is segmented into multiple functional layers including source layers, drain layers, channel layers, and memory material portions arranged in alternating stacks. Each layer performs a specific function, allowing the complex NOR array functionality to be divided into manageable components that can be manufactured and integrated systematically
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertical structures by stacking source and drain layers alternately and forming vertical word lines that extend through multiple layers. This dimensional change enables higher density while maintaining the parallel connection architecture needed for fast NOR access
2Quantity of substance
If vertical word lines are integrated with discrete memory elements in alternating stacks, then memory density and scalability are improved, but manufacturing precision requirements increase
Solution Approach 1:
Sacrificial spacer layers are formed in advance between the source and drain layers to define the precise positions where memory material portions will later be deposited. These spacers serve as templates that ensure accurate alignment and spacing, reducing the precision burden on subsequent manufacturing steps
Solution Approach 2:
The sacrificial spacer layers act as intermediary structures that facilitate the formation of the final memory structure. They are temporarily introduced to enable precise positioning of memory material portions around vertical word lines, then removed after serving their alignment function
3Reliability
If self-aligned isolation structures are implemented using sacrificial spacer layers, then reliability is improved, but device complexity increases
Solution Approach 1:
The sacrificial spacer layers are positioned and dimensioned to automatically define the isolation boundaries between adjacent memory cells. The spacers self-align with the vertical word lines and memory material portions, creating isolation structures without requiring additional alignment steps or external intervention
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and a vertical stack of discrete memory material portions laterally surrounding the vertical word line.