3D NOR Resistive Memory Layout for Parallel Cell Access
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Solution Overview
Problem
Current three-dimensional (3D) storage circuit solutions face challenges in accessing memory cells individually for read and write operations, leading to increased operation time and reduced performance due to complex peripheral circuits and interconnections, limited parallelization, and low performance of memory cells at advanced technological nodes.
Innovation Solution
A 3D memory structure connected vertically to peripheral circuits on a separate semiconductor substrate, utilizing vertical connections and optimized bonding pads to divide the memory structure into sub-arrays, enabling independent read and write operations and reducing peripheral circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional memory structure is implemented on a single substrate with NOR architecture, then parallel access to memory cells is improved, but the circuit footprint and physical complexity increase significantly due to large peripheral circuits and multiple metallization levels
Solution Approach 1:
The invention divides the memory structure into multiple independent sub-arrays, each accessible through dedicated bonding pads. This segmentation allows parallel access to multiple memory regions simultaneously while reducing the complexity of individual sub-array interconnections. Each sub-array can be independently addressed and accessed, enabling scalable parallelism without requiring a single complex peripheral circuit structure.
Solution Approach 2:
The invention transitions from planar integration to three-dimensional stacked architecture with separate substrates. Memory cells are formed in a first substrate while peripheral circuits are integrated in a second substrate, connected through vertical bonding pads and vias. This dimensional transition reduces lateral footprint and simplifies interconnection routing by utilizing the vertical dimension for signal transmission between memory and peripheral circuits.
2Adaptability or versatility
If a three-dimensional memory structure with NOR architecture is implemented on a single substrate, then read/write operation flexibility is improved, but the number of metallization levels required increases, worsening manufacturing complexity
Solution Approach 1:
The invention separates memory cell formation and peripheral circuit integration into different substrates stacked vertically. This eliminates the need for multiple complex metallization levels within a single substrate by using vertical bonding interfaces. The first substrate contains memory cells with simplified interconnections, while the second substrate contains peripheral circuits, with vertical vias and bonding pads providing the necessary connectivity without requiring extensive lateral routing layers.
Solution Approach 2:
The memory structure is divided into multiple independent sub-arrays, each with its own dedicated bonding pads and interconnection paths. This segmentation reduces the complexity of metallization routing by localizing connections within each sub-array region. The modular structure allows for simplified metallization schemes in each segment while maintaining overall system flexibility through the combination of multiple independent access paths.
3Productivity
If three-dimensional memory structures use advanced transistor nodes, then performance is improved, but the performance of memory cells relative to transistors at advanced nodes decreases
Solution Approach 1:
The invention applies different technological optimizations to different parts of the system. Memory cells utilize structures optimized for non-volatile storage characteristics, while peripheral circuits use transistors at advanced technological nodes optimized for logic performance. This local quality differentiation allows each component to operate at its optimal performance point without compromising the other, as the advanced transistors are confined to the peripheral circuit substrate rather than being required in the memory cell structure itself.
Data Source
AI summary
A data storage circuit of NOR type includes a three-dimensional memory structure, produced on a first semiconductor substrate, and comprising a plurality of memory planes, each plane forming a two-dimensional array of memory cells. Each memory cell has a selection node, a first input/output node and a second input/output node. The three-dimensional memory structure has an upper surface comprising a plurality of connectors distributed over the surface; each connector is connected to at least one among the first or second input/output nodes of a given column; a control circuit produced on a second semiconductor substrate; an interconnection structure comprising: a plurality of bonding pads placed between the control circuit and the upper surface; the plurality of bonding pads forms a periodic repetition of a unit pattern in a plane parallel to the upper surface.