3D NOR Memory Stack With Selection Transistor for Low Resistance
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Solution Overview
Problem
Existing NOR-type memory devices face challenges in scaling down due to planar device arrangements, leading to poor performance and increased resistance when stacking multiple devices, and require efficient interconnection solutions.
Innovation Solution
A NOR-type memory device with a vertical arrangement of source, gate, and drain, utilizing monocrystalline silicon as a channel material and incorporating a selection transistor to reduce wiring and resistance, achieved through a method of stacking memory device layers with a connecting portion and selection device layer, allowing for steep high source/drain doping and efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar device arrangement is used, then device layout is simple, but scaling down becomes difficult
Solution Approach 1:
The patent transitions from planar (2D) device arrangement to vertical (3D) stacking architecture. Memory device layers are stacked vertically with gate stacks extending through multiple layers, enabling scaling in the vertical dimension while maintaining manufacturability through standardized layer formation processes
2Ease of manufacture
If polycrystalline silicon is used as channel material for stacking, then device stacking is convenient, but resistance increases
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to monocrystalline silicon for the channel layer. This material parameter change reduces channel resistance while maintaining the vertical stacking architecture, as monocrystalline silicon provides superior electrical properties without compromising the stacked device structure
3Quantity of substance
If multiple devices are stacked, then integration density increases, but performance deteriorates due to increased resistance
Solution Approach 1:
The patent changes the channel material parameter to monocrystalline silicon, which maintains low resistance even in stacked configurations. This enables high integration density through vertical stacking while preserving device performance through the superior electrical properties of monocrystalline material
Solution Approach 2:
The patent implements vertical stacking of memory device layers with gate stacks extending through multiple layers. This 3D architecture increases integration density by utilizing the vertical dimension, while monocrystalline channel layers ensure low resistance paths are maintained throughout the stacked structure
4Ease of operation
If selection switch device is added, then word line control is improved, but device complexity increases
Solution Approach 1:
The patent merges the selection switch function with the existing device structure by forming selection transistors using the same vertical stacking approach as memory cells. The selection device layer is integrated with memory device layers, sharing common gate stack formation processes and reducing overall structural complexity despite adding control functionality
Data Source
AI summary
Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: a memory device layer, including a first source/drain region, a second source/drain region and a first channel region; a first gate stack extending vertically to pass through the memory device layer and including a first gate conductor layer and a memory functional layer, and a memory cell is defined at an intersection of the first gate stack and the memory device layer; a selection device layer on the memory device layer, including a third source/drain region, a fourth source/drain region and a second channel region; a second gate stack above the first gate stack and extending vertically to pass through the selection device layer; and a connecting portion electrically connecting the third source/drain region to the first gate conductor layer.