3D NOR Memory Array Pre-Charging for Faster Data Retrieval
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing high-density memory structures, such as NAND and NOR strings, face challenges with read-latency, program-disturb, and power dissipation, limiting their efficiency and scalability in data storage applications.
Innovation Solution
The implementation of NOR memory strings with horizontal active strips and vertical local word lines, allowing for pre-charging of memory cells to reduce read-latency and increase data throughput, while using quasi-volatile TFTs with modified charge-storing elements to enhance write/erase cycle endurance and reduce data retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional NAND or NOR memory strings are used, then high-density storage is achieved, but read-latency increases and data throughput decreases
Solution Approach 1:
The patent implements pre-charging of memory cells before read operations. The circuit includes pre-charge circuits that charge the memory cells in advance, so when a read operation is initiated, the data is already prepared and can be read immediately, eliminating the need to charge the cells during the read operation itself. This preliminary action significantly reduces read-latency and increases data throughput.
2Loss of energy
If conventional memory structures are used, then data storage capacity is achieved, but power dissipation increases
Solution Approach 1:
The patent segments the memory array into multiple independently controllable blocks, each with its own pre-charge circuits and control logic. This segmentation allows only the necessary blocks to be activated and pre-charged based on the access pattern, rather than pre-charging the entire memory array. Consequently, power dissipation is reduced while maintaining the required data storage capacity.
3Reliability
If read operations are performed on conventional memory, then data retrieval is achieved, but program-disturb and read-disturb conditions occur
Solution Approach 1:
The patent implements local pre-charging circuits within each memory block that are specifically tailored to the local characteristics of that block. The pre-charge voltage and timing are optimized for each local region, allowing precise control over the charge injection process. This localized approach ensures that only the selected memory cells are charged during read operations, minimizing charge injection into adjacent cells and thereby reducing program-disturb and read-disturb conditions while maintaining data integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced read-latency, lower power dissipation, and lower cost-per-bit, enabling concurrent read, write, or erase operations on multiple active strips, improving data storage efficiency and throughput.
Implementation Method 1
Capacitive-Coupled Non-Volatile Thin-Film Transistor Strings in Three Dimensional Arrays
Data Source
AI summary
A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.