3D NOR Memory Stack Layout for Density Without Read-Speed Loss

The patent transitions from a two-dimensional planar structure to a three-dimensional vertically-stacked structure. Multiple memory layers are stacked along a vertical direction, with each layer containing memory cells formed over respective substrates. This dimensional change enables significantly increased cell density while maintaining the parallel connection architecture that provides fast read speeds characteristic of NOR flash.

The patent implements a nested structure where multiple memory layers are stacked vertically, with each layer containing memory cells that are nested within the overall three-dimensional structure. The memory cells in different layers are interconnected through vertical connections, creating a nested arrangement that maximizes storage capacity within a given footprint while preserving NOR flash read performance.

By stacking memory layers vertically in the third dimension, the patent achieves high cell density without increasing the lateral footprint. The vertical stacking allows more memory cells to be packed into the same area while maintaining the parallel connection topology that enables fast read operations, thus avoiding the read speed deterioration that would normally accompany increased density.

The patent divides the memory structure into multiple discrete layers, each containing memory cells that can be independently formed and connected. This segmentation into stacked layers allows the memory array to be organized in a way that preserves the parallel connection architecture for fast reads while achieving high density through vertical arrangement of the segmented layers.