3D NOR Memory Structure with Trench Gate for High Density
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high-density storage with low energy consumption and cost efficiency due to the limitations of 2D memory cell technologies, particularly in the complexity of 3D NOR memory structures and the energy consumption associated with off-chip memory access bottlenecks.
Innovation Solution
The development of a 3D NOR array structure with 2T memory devices, featuring a trench gate architecture that reduces memory cell footprint and volume, allowing for shared source-line/bit-line design, and integration into conventional front-end-of-line (FEOL)/back-end-of-line (BEOL) processes, enabling high-density memory capacity while minimizing power consumption and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NOR memory structure is implemented to increase storage density, then memory capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from traditional 2D memory cell arrays to a 3D stacked architecture where memory cells are arranged in multiple vertical layers. Each layer contains memory cells formed by intersecting bit lines and word lines, with select gates controlling access to specific layers. This vertical stacking enables significantly higher storage density by utilizing the third dimension (height) rather than only expanding in the planar direction.
Solution Approach 2:
The 3D memory structure is divided into multiple independent layers, with each layer containing complete sets of bit lines, word lines, and select gates. This segmentation allows each layer to function as an independent memory plane that can be accessed and controlled separately, simplifying the overall system architecture while achieving high density through vertical stacking.
2Quantity of substance
If memory cell size is scaled down to increase integration density, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Instead of continuing to scale down critical dimensions in the 2D plane, the patent achieves higher integration density by stacking multiple memory cell layers vertically. This approach shifts the density improvement from lateral scaling to vertical stacking, thereby avoiding the escalating manufacturing precision requirements associated with sub-10nm critical dimensions.
Solution Approach 2:
Multiple memory cell layers are nested vertically one above another, with each layer containing complete functional elements (bit lines, word lines, select gates). This nesting approach allows high integration density to be achieved by stacking identical functional units in the vertical direction, maintaining manufacturability while dramatically increasing total storage capacity.
3Quantity of substance
If off-chip memory access is used to achieve mass capacity, then storage capacity is improved, but energy consumption increases
Solution Approach 1:
The patent integrates multiple memory cell layers and their associated select gates, bit lines, and word lines onto a single chip, creating a unified 3D memory array. This on-chip integration eliminates the need for off-chip memory access, thereby removing the energy-consuming data transfer bottleneck between separate memory chips and processing units while maintaining high storage capacity.
Solution Approach 2:
By implementing a 3D stacked memory architecture on a single chip, the patent achieves mass storage capacity without requiring multiple off-chip memory devices. The vertical stacking of memory planes within one chip reduces the physical distance data must travel and eliminates inter-chip communication overhead, significantly reducing power consumption compared to traditional off-chip memory solutions.
Data Source
AI summary
A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.