3D NOR String Arrays in Segmented Stacks
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Solution Overview
Problem
The challenge in manufacturing non-volatile NOR-type memory strings in 3-dimensional semiconductor structures lies in the difficulty of anisotropically etching narrow trenches due to tall and narrow stacks, which are mechanically unstable and exhibit high resistance and delayed response times due to vertical local word-lines, requiring innovative interconnect schemes distinct from those used in NAND strings.
Innovation Solution
The solution involves forming memory modules with reduced-height active stacks, where each module consists of two or more sets of half-height active stacks with local word lines connected through both top and bottom global word lines, reducing the aspect ratio of etched trenches and stabilizing the structure, while employing a unique interconnect scheme that connects substrate circuitry to local word lines via both top and bottom global word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If tall and narrow stacks of active layers are used to increase memory density, then memory capacity is improved, but anisotropic etching of narrow trenches becomes increasingly difficult and mechanically unstable
Solution Approach 1:
The patent divides the tall stack of active layers into multiple segments separated by isolation layers. Each segment contains a subset of active layers (e.g., 4-8 layers per segment) rather than one continuous tall stack, making the etching process more manageable and mechanically stable while preserving overall memory capacity through vertical stacking of multiple segments.
2Quantity of substance
If tall and narrow stacks of active layers are used to increase memory density, then memory capacity is improved, but mechanical stability deteriorates requiring supporting struts
Solution Approach 1:
The patent introduces isolation layers that physically segment the tall stack into shorter, more stable segments. This segmentation reduces the height-to-width ratio of each segment, improving mechanical stability without requiring additional supporting struts, while the vertical arrangement of multiple segments maintains high memory capacity.
3Ease of operation
If vertical local word-lines are formed in long and narrow trenches to access memory strings, then memory addressing is enabled, but resistance and RC time constants increase delaying response time
Solution Approach 1:
The patent segments the vertical local word-lines into multiple shorter segments corresponding to the segmented active layers. Each segment connects to a subset of memory strings, reducing the length and resistance of individual word-line trenches. This segmentation decreases RC time constants and improves response time while maintaining full memory addressing capability through the hierarchical interconnect structure.
4Ease of manufacture
If segmented stacks are used to reduce etching aspect ratio, then manufacturing ease is improved, but interconnect scheme complexity increases compared to NAND strings
Solution Approach 1:
The patent employs segmented stacks with isolation layers to reduce etching aspect ratios to manageable levels. While this creates a more complex interconnect scheme compared to traditional NAND strings, the segmentation enables precise control over trench depth and width, improving manufacturing yield and enabling new memory cell architectures that would be impossible with single tall stacks.
Data Source
AI summary
A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.