3D NOR Memory String Layout for Isolation and Density
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Solution Overview
Problem
Existing 3-D NOR memory arrays face challenges in efficiently forming thin-film storage transistors within a 3-dimensional memory structure, particularly in creating high-density memory circuits with optimal conductivity and isolation between memory strings.
Innovation Solution
A process involving the formation of thin-film storage transistors within shafts or trenches of a semiconductor structure, using semiconductor layers, charge-trapping layers, and conductor layers to create common bit and source lines, channel regions, and gate electrodes, with isolation materials ensuring efficient electrical separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thin-film storage transistors are formed in shafts or trenches of a 3-dimensional memory structure, then manufacturing precision and isolation between memory strings are improved, but device complexity increases
Solution Approach 1:
The memory structure is divided into multiple shafts and trenches that are arrayed in regular patterns along orthogonal directions. Each shaft/trench contains isolated memory strings, creating natural separation between adjacent memory cells. This segmentation approach improves isolation between memory strings while maintaining a systematic, scalable structure that manages complexity through repetition and modularity.
Solution Approach 2:
Different regions of the structure serve different functions: shafts contain memory strings with specific conductivity types, trenches provide isolation regions with dielectric materials, and active multi-layers are positioned at specific depths. This local differentiation optimizes each region for its specific purpose, improving overall manufacturing precision and electrical isolation while organizing complexity through functional specialization.
2Quantity of substance
If multiple active multi-layers are stacked along a direction normal to the substrate surface, then memory density is improved, but manufacturing complexity increases
Solution Approach 1:
The memory structure transitions from planar to three-dimensional by stacking multiple active multi-layers along the vertical direction (normal to the substrate surface). Each multi-layer contains semiconductor layers separated by dielectric materials, creating a vertical stack that dramatically increases memory density. The regular arraying of shafts and trenches through all layers provides a systematic approach to managing the complexity of multi-layer fabrication.
Solution Approach 2:
Multiple active multi-layers are nested vertically within the same footprint area, with each layer containing semiconductor layers and dielectric materials in a repeating pattern. The shafts and trenches extend through all nested layers, providing continuous structural support and electrical isolation. This nesting approach maximizes memory density within the available volume while using a compact, repeating structural motif to manage fabrication complexity.
3Ease of manufacture
If shafts and trenches are arrayed in regular patterns along orthogonal directions, then manufacturing ease is improved, but space utilization decreases
Solution Approach 1:
Shafts and trenches serve as intermediary structures that facilitate the fabrication process. The shafts contain the memory strings while trenches provide isolation between adjacent shafts. This intermediary structure of regularly arrayed shafts and trenches simplifies manufacturing by providing a systematic template for material deposition and patterning, even though it reduces the fraction of area dedicated to active memory elements compared to a completely planar design.
Data Source
AI summary
A process for manufacturing a 3-D NOR memory array provides thin-film storage transistors of each NOR memory string in either shafts or portions of a trench between adjacent shafts.