3D NOR String Arrays in Segmented Memory Stacks
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Solution Overview
Problem
The challenge in manufacturing non-volatile NOR-type memory strings in 3-dimensional semiconductor structures is the difficulty in anisotropically etching narrow trenches due to tall and narrow stacks, which results in mechanical instability and high resistance in vertical local word-lines, delaying response time for memory strings far from global word lines.
Innovation Solution
The solution involves forming memory modules with two or more sets of active strips as half-height stacks, connected by global interconnect conductors, reducing the aspect ratio of etched trenches and stabilizing the structure, while using both top and bottom global word lines to connect local word lines to substrate circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If tall and narrow stacks of active layers are used to increase memory density, then storage capacity is improved, but anisotropic etching of narrow trenches becomes difficult and mechanical stability deteriorates
Solution Approach 1:
The memory structure is divided into multiple segments along the vertical direction, with each segment containing a subset of active layers. Isolation layers are inserted between segments to create mechanically stable, shorter stacks while maintaining high overall density. This segmentation approach allows etching of manageable trench depths without compromising total storage capacity.
Solution Approach 2:
The patent introduces a lateral dimension for interconnect routing by placing global word lines and bit lines in horizontal planes between stacked memory segments. This dimensional transition reduces vertical trench requirements and improves mechanical stability while maintaining electrical connectivity across all memory layers.
2Quantity of substance
If tall and narrow stacks are used to increase memory density, then storage capacity is improved, but resistance in vertical local word-lines increases and response time deteriorates
Solution Approach 1:
Vertical local word lines are divided into shorter segments corresponding to each memory segment, with global word lines providing horizontal interconnect paths. This segmentation reduces the length and resistance of individual vertical word line segments, improving signal propagation speed and response time while maintaining access to all memory layers.
Solution Approach 2:
Global word lines are routed horizontally between memory segments rather than vertically through the entire stack. This dimensional change creates shorter, lower-resistance electrical paths for addressing memory strings, reducing RC time constants and improving response time for distant memory locations.
3Stability of the object's composition
If segmented stacks with isolation layers are used to improve mechanical stability, then structural integrity is improved, but device complexity increases
Solution Approach 1:
The isolation layers serve multiple functions simultaneously: they provide mechanical support to stabilize tall stacks, enable segmentation for easier etching, facilitate lateral interconnect routing, and reduce electrical resistance of word lines. This multi-functionality reduces overall device complexity despite the segmented structure.
Solution Approach 2:
The patent combines vertical stacking with lateral segmentation and interconnect routing into a unified three-dimensional architecture. By merging these functions into a single integrated structure rather than separate components, the overall device complexity is managed while achieving mechanical stability and improved electrical performance.
Data Source
AI summary
A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.