3D NOR Memory Array Layout With Wider Source/Drain Lines
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Solution Overview
Problem
3D NOR type memory arrays face reliability issues due to damage to the channel and memory layers during manufacturing, primarily caused by the direct overlap of masking structures over these layers, leading to incomplete or damaged memory cells.
Innovation Solution
A method is introduced where a first trench is formed within a stack of dummy gate electrode layers, filled with a sacrificial material, and then widened to create openings that allow for the selective removal of dielectric layers without damaging the channel or memory layers, followed by the deposition of gate electrode layers and subsequent removal of the sacrificial material, ensuring complete filling of the trench with memory, channel, and dielectric layers, and the formation of source and drain conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If masking structures are directly overlapped over channel and memory layers during manufacturing, then manufacturing process is simplified, but channel and memory layers are damaged
Solution Approach 1:
The patent introduces a preliminary protective action by forming a sacrificial material layer over the channel and memory layers before depositing the masking structure. This preliminary protective layer prevents direct contact between the masking structure and the sensitive layers, thereby preventing damage while maintaining the simplified manufacturing process.
Solution Approach 2:
The sacrificial material layer acts as an intermediary between the masking structure and the channel/memory layers. This intermediate layer allows the masking structure to be deposited and patterned without directly damaging the underlying sensitive layers, and can be selectively removed later to complete the device formation.
2Quantity of substance
If memory density is increased by transitioning from 2D to 3D memory arrays, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming the sacrificial material layer, depositing and patterning the masking structure, and selectively removing the sacrificial material. This segmentation allows each step to be optimized independently, making the complex 3D memory manufacturing process more manageable and controllable.
Solution Approach 2:
The sacrificial material serves as a temporary intermediary structure that enables the formation of complex 3D memory arrays. It provides a framework for depositing gate electrode layers and defining cell structures in three dimensions, and is removed after serving its structural purpose, simplifying the overall manufacturing complexity.
3Power
If source/drain conductive lines are made wider to improve current flow, then electrical performance is improved, but area occupied by conductive lines increases
Solution Approach 1:
The patent transitions from planar 2D conductive lines to vertically-oriented 3D conductive structures that extend through multiple gate electrode layers. This dimensional change allows the source/drain lines to provide enhanced current flow paths in the vertical direction while occupying less horizontal area, thereby improving electrical performance without increasing device footprint.
Solution Approach 2:
The wider source/drain conductive lines are nested within the three-dimensional memory structure, surrounded by channel layers and gate electrode layers. This nesting arrangement allows the conductive lines to have increased width for better current flow while being efficiently space-utilized within the vertical stack, minimizing the area occupied.
Data Source
AI summary
In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.