3D Non-Volatile Memory Junction Formation via Selective Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional non-volatile memory devices face challenges in achieving optimal performance characteristics, particularly in the integration of vertical transistor structures and the formation of precise junction regions, which affect the integrity and capacity of these devices.
Innovation Solution
A method involving the formation of a stack structure on a semiconductor substrate, with a gap-filling insulation layer that is selectively etched to define a preliminary junction region, and a channel pillar structure including a memory layer, channel layer, and junction region, where the uppermost gate has a greater thickness than the rest, ensuring accurate positioning of the junction interface within the gate length range to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical transistor structure is adopted to increase integration degree, then device capacity and storage density are improved, but manufacturing precision and structural integrity become more difficult to maintain
Solution Approach 1:
The device is divided into multiple functional layers including charge trapping layer, tunnel insulation layer, blocking insulation layer, and channel layer, each formed through separate deposition processes. This segmentation allows precise control of each layer's properties while maintaining overall structural integrity in the vertical configuration
Solution Approach 2:
The charge trapping layer and tunnel insulation layer are formed on the channel layer before final device completion. This preliminary formation of critical layers ensures proper charge storage functionality is established early in the manufacturing process, enabling subsequent steps to focus on interconnect formation without compromising structural integrity
2Reliability
If junction regions are formed to enhance performance characteristics, then device functionality is improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The gap-filling insulation layer serves as an intermediary material that is selectively removed to define the junction region. This intermediary approach simplifies the manufacturing process by providing a clear mask for ion implantation, reducing the complexity of directly forming precise junction regions while maintaining reliable device performance
Solution Approach 2:
Ion implantation is used to modify the electrical parameters of the channel layer, creating the junction region with controlled doping concentration and depth. This parameter change approach allows precise control of junction characteristics without complex lithography steps, reducing manufacturing complexity while enhancing device reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the structural integrity and performance characteristics of three-dimensional non-volatile memory devices by accurately forming junction regions and channel pillars, thereby enhancing data storage capacity and processing efficiency.
Implementation Method 1
The gap-filling insulation layer may be selectively removed to define a preliminary junction region
Implementation Method 2
Ions may be implanted into a target position of the gap-filling insulation layer
Data Source
AI summary
In a method of manufacturing a non-volatile memory device, a stack structure may be formed on a semiconductor substrate. The stack structure may be etched to form a contact hole through the stack structure. The contact hole may be filled with a gap-filling insulation layer. Ions may be implanted into a target position of the gap-filling insulation layer. The gap-filling insulation layer may be selectively removed to define a preliminary junction region. A junction region may be formed in the preliminary junction region.


