3D Nonvolatile Memory Device Fabrication Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The conventional method for fabricating 3D nonvolatile memory devices is complex, leading to non-uniform channel widths and difficulties in controlling threshold voltage due to high aspect ratio trenches and increased integration density, which complicates the alignment of channels and increases fabrication costs.
Innovation Solution
A 3D nonvolatile memory device with alternately stacked channel structures and interlayer dielectric layers, along with word and column select lines, simplifies the fabrication process by forming channel structures with uniform widths and pillar-shaped select gates, allowing for easier control of threshold voltage and reduced fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional sequential formation of lower select transistor, memory cells, and upper select transistor is used, then 3D vertical channel structure is achieved, but fabrication process becomes complex and channel width uniformity deteriorates
Solution Approach 1:
The patent merges the formation of lower select transistor, memory cells, and upper select transistor into a single simultaneous fabrication step. Multiple channel structures are formed together in one etching process rather than sequentially, which simplifies the fabrication process and ensures uniform channel widths across all structures.
Solution Approach 2:
The patent segments the channel structures into multiple independent vertical channels that are formed simultaneously. Each channel structure includes its own select transistor, memory cell, and associated components, allowing parallel fabrication while maintaining uniformity through single-process formation.
2Productivity
If high aspect ratio trenches are used to achieve vertical channel structures, then integration density is improved, but threshold voltage control becomes difficult
Solution Approach 1:
The patent applies different material compositions and doping profiles to different regions of the channel structures. The select transistor regions have different doping concentrations compared to memory cell regions, allowing optimized threshold voltage control for each functional area while maintaining the high aspect ratio vertical structure for integration density.
3Productivity
If increased integration density is achieved through vertical stacking, then device capacity is improved, but alignment of channels becomes more difficult
Solution Approach 1:
The patent forms all channel structures, including lower select transistor channels, memory cell channels, and upper select transistor channels, in a single etching step from the substrate. This preliminary simultaneous formation ensures precise alignment of all channels before subsequent processing steps, eliminating alignment errors that would occur with sequential formation.
Data Source
AI summary
A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction.