3D Non-Volatile Memory Fabrication via Selective Protective Layers
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Solution Overview
Problem
The complexity of fabricating three-dimensional non-volatile memory devices with vertically stacked memory cells poses challenges in simplifying the fabrication process, particularly in forming memory cells and channel regions for select transistors without damaging interlayer dielectric layers.
Innovation Solution
A method involving the stacking and etching of interlayer dielectric and gate conductive layers to form cell and select transistor channel holes, with the use of protective and capping layers to prevent damage and enable simultaneous formation of memory cells and select transistors, including the formation of a memory layer for charge trapping and insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processes are used to form memory cells and select transistor channel regions, then each component can be formed with dedicated optimization, but the fabrication process becomes complicated and less efficient
Solution Approach 1:
The patent combines the formation of memory cell channel holes and select transistor channel holes into a single etching process. By using a unified mask pattern that defines both cell and select transistor regions, the method simultaneously forms both types of channel holes through one etching step, thereby reducing process complexity while maintaining formation precision through carefully controlled etching parameters and mask design
2Productivity
If interlayer dielectric layers are etched to form channel holes, then memory cells and transistors can be formed, but the interlayer dielectric layers may be damaged
Solution Approach 1:
The patent applies a protective layer to the interlayer dielectric layers before the etching process that forms channel holes. This preliminary protection prevents damage to the dielectric layers during etching, ensuring their integrity is maintained while still allowing the necessary channel holes to be formed for memory cell and transistor fabrication
3Ease of manufacture
If channel holes are formed early in the process, then subsequent layer formation can proceed, but already opened memory cell regions need protection during later channel formation
Solution Approach 1:
The patent forms a protective layer over the interlayer dielectric layers before etching channel holes, and this protective layer remains in place during subsequent processing steps. When select transistor channel holes are formed later, the protective layer continues to shield the already-opened memory cell regions, preventing accidental damage while allowing clean formation of the select transistor channels
Solution Approach 2:
The protective layer acts as an intermediary element between the etching process and the interlayer dielectric layers. It mediates the interaction by providing a sacrificial barrier that protects sensitive regions during etching, can be selectively removed or retained as needed, and does not interfere with the ultimate formation of functional channel holes
Data Source
AI summary
A method for fabricating a non-volatile memory device includes repeatedly stacking interlayer dielectric layers and gate conductive layers on a substrate; etching the interlayer dielectric layers and the gate conductive layers to form cell channel holes that expose the substrate, forming a protective layer along a resultant structure, forming a capping layer on the protective layer to fill the cell channel holes, planarizing the protective layer and the capping layer until an uppermost one of the interlayer dielectric layers is exposed, forming a gate conductive layer for select transistors and an interlayer dielectric layer for select transistors on a resultant structure, etching the interlayer dielectric layer and the gate conductive layer, to form select transistor channel holes that expose the capping layer while removing the capping layer buried in the cell channel holes, and removing the protective layer.