3D Non-Volatile Memory Stacked Structure for Integration Density
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Solution Overview
Problem
The integration density of two-dimensional non-volatile memory devices is limited, leading to the development of three-dimensional structures, but these face challenges in operational reliability and manufacturing complexity.
Innovation Solution
A semiconductor device with a stacked structure featuring channel layers, a well plate, source layers, and connection structures, including contact patterns and isolation patterns, to enhance reliability and simplify manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional non-volatile memory devices are used, then manufacturing processes are simple, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with each layer containing memory cells formed over the substrate. This dimensional change enables significantly higher integration density while maintaining compatible manufacturing processes.
2Quantity of substance
If three-dimensional non-volatile memory devices are used, then integration density is improved, but operational reliability deteriorates
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete memory cell layers stacked vertically. Each layer contains complete memory cells with source, drain, gate, and insulating regions. This segmentation allows each layer to function independently, improving operational reliability while achieving high integration density through vertical stacking.
Solution Approach 2:
Interlayer insulating layers are introduced between adjacent memory cell layers to provide electrical isolation and structural support. These intermediary layers prevent unwanted electrical interactions between stacked layers, thereby improving operational reliability of the three-dimensional memory device.
3Quantity of substance
If three-dimensional non-volatile memory devices are used, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
Sacrificial structures are formed in advance before the memory cell layers are stacked. These sacrificial structures serve as temporary support elements during the stacking process and are later removed to create the final memory structure. This preliminary action simplifies the manufacturing of complex three-dimensional structures by providing temporary structural guidance.
Solution Approach 2:
Multiple memory cell layers are nested vertically one on top of another, with each layer containing complete memory cell structures. The nested stacking approach allows systematic formation of three-dimensional memory arrays, reducing manufacturing complexity compared to attempting to form the entire structure in a single process step.
Data Source
AI summary
A semiconductor device includes a stacked structure, channel layers passing through the stacked structure, a well plate located under the stacked structure, a source layer located between the stacked structure and the well plate, a connection structure coupling the channel layers to each other and including a first contact contacting the source layer and a second contact contacting the well plate, and an isolation pattern insulating the source layer and the well plate from each other.