3D Non-Volatile Memory Crossbar Integration

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Solution Overview

Problem

The challenge lies in achieving high integration and reliability in 3D non-volatile memory devices while overcoming the limitations of 2D semiconductor memory devices, including unstable processes and product reliability issues as they approach scaling limits.

Innovation Solution

A 3D non-volatile memory device is designed with conductive lines and planes arranged in a 3D structure, incorporating non-volatile data storage layers made of phase change materials, variable resistive materials, or programmable metallization cells, along with selection diode layers and insertion electrodes, to enable high integration and reliable fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If 2D semiconductor memory devices are used to achieve high integration, then the integration level is improved, but the process stability and product reliability deteriorate as scaling limits are approached

Engineering Contradiction:
Improveintegration levelVSAvoidprocess stability and product reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from traditional 2D memory architecture to a 3D crossbar structure where conductive lines and planes intersect in three-dimensional space. This dimensional change allows memory cells to be formed at intersection points without requiring continuous scaling of 2D features, thereby maintaining process stability while achieving higher integration through vertical stacking and spatial arrangement of conductive elements

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If fine pattern forming technique level is increased to improve integration, then the integration level is improved, but the difficulty of arranging semiconductor fabricating equipments and processes increases

Engineering Contradiction:
Improveintegration levelVSAvoidcomplexity of fabricating equipments and processes
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory device is segmented into multiple conductive lines extending in a first direction and multiple conductive planes extending in a second direction perpendicular to the first. This segmentation allows each conductive element to be formed using standard fabrication processes, and the overall high integration is achieved through the systematic arrangement and intersection of these segmented conductive elements in 3D space

Inventive Principle:
Principle #1Segmentation

3Productivity

If 3D structure is adopted to overcome integration limits, then the integration level is improved, but the process stability and product reliability worsen

Engineering Contradiction:
Improveintegration levelVSAvoidprocess stability and product reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges conductive lines and conductive planes to form a crossbar structure where memory cells are created at their intersections. This merging approach allows the 3D structure to be built using conventional conductive material deposition and patterning processes, maintaining process stability while achieving high integration through the combined spatial arrangement of conductive elements rather than requiring entirely new 3D fabrication techniques

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9735203B23-dimensional (3D) non-volatile memory device and method of fabricating the same
Publication Date: 2017.08.15 SK HYNIX INC
  • US9735203B2 patent drawing
  • US9735203B2 patent drawing
  • US9735203B2 patent drawing

AI summary

Provided are 3D non-volatile memory devices and methods of fabricating the same. A 3D non-volatile memory device according to an embodiment of the present invention includes a plurality of conductive lines, which are separated from one another in parallel; a plurality of conductive planes, which extend across the plurality of conductive lines and are separated from one another in parallel; and non-volatile data storage layer patterns, which are respectively arranged at regions of intersection at which the plurality of conductive lines and the plurality of conductive planes cross each others.