3D Vertical NVM Structure for Dual NOR and NAND Operation
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Solution Overview
Problem
Current semiconductor memory technologies require different manufacturing processes for NOR and NAND flash memories, making it impractical to use 3D NVMs as both NOR and NAND types due to size and cost constraints, and existing attempts to adapt one type to the other have been non-competitive in speed or cost.
Innovation Solution
The development of novel 3D NVM structures using vertical transistors made of semiconductor pillars, allowing for the same footprint as competitive NAND-type cells, enabling operation as either NOR or NAND flash without speed or cost disadvantages, with a memory controller designed to interpret both operational codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If 3D NVM structures are designed for NOR-type operation, then random access capability is achieved, but cell size increases by 2-3 times compared to NAND-type
Solution Approach 1:
The patent transitions from planar 2D cell layouts to three-dimensional vertical structures. Memory cells are stacked in the vertical dimension with multiple layers of bit lines, word lines, and charge storage regions, enabling NOR-type random access functionality while maintaining compact footprint by utilizing the third dimension for cell organization.
Solution Approach 2:
The 3D NVM structure is designed to provide universal functionality that can operate in both NOR and NAND modes. The same physical structure supports different access schemes through configurable control logic, eliminating the need for separate specialized designs and allowing the cell to serve multiple purposes without size penalty.
2Ease of manufacture
If 3D NVM structures are designed for NAND-type operation, then manufacturing cost is reduced, but access speed decreases and external trigger is required
Solution Approach 1:
By stacking memory cells vertically and implementing three-dimensional interconnect structures, the patent achieves high-density NAND-type organization with improved speed characteristics. The vertical architecture reduces signal path lengths and enables parallel operation of multiple cell strings, thereby maintaining fast access speeds while keeping manufacturing costs low through efficient process integration.
3Reliability
If different manufacturing processes are used for NOR and NAND flash memories, then each type can be optimized for its specific operation, but manufacturing complexity and cost increase
Solution Approach 1:
The patent develops a unified manufacturing process that produces a universal 3D NVM structure capable of operating in both NOR and NAND modes. The same fabrication steps, materials, and device structures are used regardless of the intended access mode, with the final configuration determined by control logic rather than manufacturing differences. This eliminates the need for maintaining separate process lines while preserving operation-specific optimization through software/firmware control.
4Ease of operation
If 3D NVM cell size is increased to achieve NOR-type operation, then random access is enabled, but chip area and cost per bit increase
Solution Approach 1:
The patent implements multi-layer stacking in the vertical dimension where multiple layers of bit lines, word lines, and charge storage regions are stacked above each other. This three-dimensional organization enables NOR-type random access functionality while achieving high density by utilizing vertical space, thereby reducing the horizontal chip area required and lowering cost per bit compared to traditional 2D NOR structures.
Data Source
AI summary
Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.