3D Vertical NVM Layout for NOR-NAND Memory Flexibility
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Solution Overview
Problem
Current semiconductor memory technologies require different manufacturing processes for NOR and NAND flash memories, making it impractical to switch between the two without increasing cell size and manufacturing complexity, and existing attempts to adapt NAND or NOR cells have been non-competitive due to cost and speed issues.
Innovation Solution
The development of 3D nonvolatile memory (NVM) structures using vertical transistors made of semiconductor pillars, allowing for NOR-type memory cells with the same footprint as competitive NAND-type cells, enabling operation as either NOR or NAND flash without speed or cost disadvantages, through a properly designed memory controller that interprets both operational codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If NOR-type memory cells are used for code storage, then random access capability is improved, but cell size increases by 2-3 times and per-bit cost increases
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to vertical 3D architecture by stacking multiple memory cell layers above a common bit line. This dimensional change allows NOR-type cells to achieve random access capability while reducing the horizontal footprint and increasing storage density, directly resolving the contradiction between access capability and cell size.
2Quantity of substance
If NAND-type memory cells are used for mass data storage, then storage density is improved, but access speed deteriorates due to sequential access requirement
Solution Approach 1:
By implementing vertical stacking of memory cells in 3D, the patent enables parallel access to multiple cells simultaneously along the vertical dimension while maintaining high storage density. This resolves the contradiction by allowing NAND-type cells to provide both high density and improved access speed through vertical parallelism.
Solution Approach 2:
The patent divides the memory array into multiple vertically stacked cell layers, each accessible through the common bit line. This segmentation allows selective access to specific layers while maintaining high density, enabling parallel operations that improve access speed without sacrificing storage capacity.
3Reliability
If different manufacturing technologies are developed for NOR and NAND flashes, then each type can be optimized for its specific application, but manufacturing complexity and cost increase
Solution Approach 1:
The patent creates a universal 3D memory cell architecture that can be configured to exhibit either NOR or NAND characteristics through programming and control circuit design, rather than requiring separate physical structures. This multi-functional approach allows a single manufacturing process to produce memory suitable for both code storage and mass data storage applications, reducing complexity while maintaining application-specific optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for flexible operation as either NOR or NAND flash with no speed disadvantage for NOR and no cost disadvantage for NAND, using a single technology node, and enables part of the 3D NVM to be operated as NOR and the rest as NAND with programmable configurations, maintaining stored values without alteration.
Implementation Method 1
EPROMs (erasable programmable read-only memories) are programmed by electron tunneling, and erased by ultraviolet illumination. EEPROMs (electrically erasable programmable read-only memories) use electron tunneling for erase and program operations
Implementation Method 2
Flash memories are like EEPROMs except programming may rely on hot-carrier effects and the erase operation erases a block of memory cells simultaneously
Data Source
AI summary
Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.