3D Non-Volatile Memory Device With P-Type Well Area
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Solution Overview
Problem
Conventional 3D non-volatile memory devices have complex fabrication processes, degraded performance due to amorphous or polycrystalline silicon channels, high source area resistance, and slow erase voltage transfer, leading to reliability and power consumption issues.
Innovation Solution
A 3D non-volatile memory device with a plate-type lower select line, a lower select transistor, stacked memory cells, an upper select transistor, and a line-type common source line, where the well area between the select transistor and common source line has a different conductive type, allowing for improved control of threshold voltage and erase operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent processes are performed on cell area and peripheral circuit area to form lower select transistor, memory cells, and upper select transistor, then the memory device can be fabricated with conventional processes, but the fabricating process becomes complex and manufacturing cost increases
Solution Approach 1:
The patent merges the fabrication processes of the cell area and peripheral circuit area into a unified process. The lower select transistor is formed in the peripheral circuit area using the same processes as the memory cells in the cell area, eliminating the need for separate independent processes. This integration simplifies the overall fabrication process while maintaining device performance.
2Ease of manufacture
If channels of select transistors are formed of amorphous silicon or polycrystalline silicon, then the transistor can be fabricated with standard processes, but the on/off characteristics are degraded and threshold voltage control becomes difficult
Solution Approach 1:
The patent changes the material parameter of the channel from amorphous or polycrystalline silicon to single-crystal silicon. This parameter change fundamentally improves the on/off characteristics and threshold voltage control while still being compatible with standard semiconductor fabrication processes through selective epitaxial growth or other single-crystal formation techniques.
3Ease of manufacture
If N-type ion impurities are implanted into substrate to form source area, then the source area can be formed with conventional doping processes, but the source area has high resistance causing read operation errors
Solution Approach 1:
The patent changes the doping type parameter from N-type to P-type for the source area. This parameter change reduces the resistance of the source area, preventing read operation errors while still using conventional ion implantation doping processes. The P-type doping is achieved through standard phosphorus or boron implantation techniques.
4Ease of manufacture
If conventional fabrication processes are used for 3D non-volatile memory device, then the device can be manufactured with existing technology, but the erase voltage transfer speed is slow degrading device performance
Solution Approach 1:
The patent changes the conductive type parameter of the well area to P-type, which creates a more favorable electrical field distribution for erase voltage transfer. This parameter change accelerates the erase voltage transfer speed by reducing depletion region effects and improving carrier mobility, while still using conventional well formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Simplifies the fabrication process, enhances on/off characteristics, reduces resistance errors, and increases erase operation speed while reducing power consumption by using a P-type well area to efficiently transfer erase voltage.
Implementation Method 1
the well area between the select transistor and common source line has a different conductive type, allowing for improved control of threshold voltage and erase operation speed
Data Source
AI summary
A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.