3D Nonvolatile Memory Resistance Change Structure
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in maintaining structural stability and reliability due to increasing integration and decreasing design rules, particularly in storing signal information efficiently using charge storage structures.
Innovation Solution
A nonvolatile memory device with a resistance change structure is developed, featuring a substrate with alternately stacked channel and interlayer insulation layers, resistance change layers, and gate insulation layers, along with gate line structures that apply voltage to form conductive channels and manage resistance states for signal storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge storage structures are used in flash memory devices, then signal information can be stored, but structural stability and reliability deteriorate due to increasing integration and decreasing design rules
Solution Approach 1:
The patent replaces the traditional charge storage mechanism (relying on physical charge trapping in insulation layers) with a resistance change mechanism. The memory device uses a resistance change layer that switches between high and low resistance states to store information, eliminating the need for complex charge storage structures and their associated reliability issues under scaling.
Solution Approach 2:
The patent utilizes changes in resistance state (from high resistance to low resistance and vice versa) as the fundamental storage mechanism. By applying voltages to the gate line structures, the resistance of the resistance change layer is modulated to represent binary states, providing a simpler and more reliable alternative to charge storage under continued scaling.
2Quantity of substance
If traditional flash memory structures are used, then charge storage is achieved, but device complexity increases with scaling
Solution Approach 1:
The patent extracts and removes the complex charge storage structure (charge tunneling layer, charge trap layer, charge barrier layer) from the memory device. By eliminating these layers and using only a resistance change layer with gate line structures, the device achieves memory functionality with significantly reduced structural complexity.
Solution Approach 2:
The complex multi-layer charge storage system is replaced with a simpler resistance change layer system. The gate line structures directly control the resistance state of the memory layer without requiring charge tunneling or trapping mechanisms, thereby reducing device complexity while maintaining storage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reliable and efficient storage of signal information by varying resistance states in a nonvolatile manner, improving the structural stability and reliability of memory operations.
Implementation Method 1
A gate voltage may be applied to the plurality of gate line structures to form a conductive channel in a channel layer pattern of the at least one channel structure
Implementation Method 2
a resistance change layer disposed over the substrate and on at least a portion of one sidewall surface of the channel structure
Data Source
AI summary
A nonvolatile memory device includes a substrate having an upper surface and a channel structure disposed over the substrate. The channel structure includes at least one channel layer pattern and at least one interlayer insulation layer pattern, which are alternately stacked in a first direction perpendicular to the upper surface, and the channel structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a resistance change layer disposed over the substrate and on at least a portion of one sidewall surface of the channel structure, a gate insulation layer disposed over the substrate and on the resistance change layer, and a plurality of gate line structures disposed over the substrate, each contacting a first surface of the gate insulation layer and disposed to be spaced apart from each other in the second direction.