3D Nonvolatile Memory Fabrication via Sacrificial Layer Trenches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in fabricating vertically stacked nonvolatile memory devices lies in forming transistors that effectively control memory cells while reliably connecting wiring, as existing methods face difficulties in configuring the device structure.
Innovation Solution
A method involving the sequential stacking of interlayer dielectric films, sacrificial layers, and resistance variable layers on a semiconductor substrate, with the formation of electrodes and channel layers, followed by the creation of insulation layers and trench structures to facilitate the formation of transistors that control memory cells in predetermined units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If vertically stacked nonvolatile memory device structure is adopted to improve integration level, then integration level is improved, but difficulty in forming transistors and connecting wiring increases
Solution Approach 1:
The memory device is divided into multiple functional layers stacked vertically: interlayer dielectric films (112, 122, 132), sacrificial layers (119, 129, 139), resistance variable layers (141), channel layers (143), and insulation layers (144). Each layer serves a specific function, allowing complex functionality to be achieved through modular vertical stacking rather than horizontal integration, thus improving integration level while managing complexity through systematic layering.
Solution Approach 2:
The patent transitions from planar (2D) memory structure to vertically stacked (3D) structure. Memory cells are arranged in vertical columns with multiple interlayer dielectric films and functional layers stacked along the thickness direction, enabling higher integration density by utilizing the third dimension (vertical space) rather than expanding horizontally.
2Ease of operation
If transistors are formed to control memory cells in predetermined units, then control capability is improved, but manufacturing complexity increases
Solution Approach 1:
Sacrificial layers (119, 129, 139) are formed in advance during the stacking process to define future transistor regions. These sacrificial layers are removed later to create trenches, leaving behind pre-formed insulation layers (144) and channel layers (143) that are already positioned correctly for transistor formation. This preliminary positioning simplifies subsequent manufacturing steps.
Solution Approach 2:
Sacrificial layers act as intermediary structures during fabrication. They are temporarily introduced to define spatial relationships between components, then removed to create the final transistor structure. This intermediary approach allows complex transistor geometries to be formed through simpler sequential steps rather than attempting to form the final structure directly.
3Manufacturing precision
If multiple interlayer dielectric films and sacrificial layers are stacked sequentially, then structural precision is improved, but number of fabrication steps increases
Solution Approach 1:
Multiple functions are merged into single fabrication steps where possible. For example, trenches are formed to simultaneously create wiring paths and expose sacrificial layers for removal. The stacking of interlayer dielectric films (112, 122, 132) with sacrificial layers (119, 129, 139) is performed in an integrated sequence rather than separate operations, reducing the total number of fabrication steps while maintaining precise layer alignment.
Solution Approach 2:
The interlayer dielectric films (112, 122, 132) serve multiple functions: electrical insulation between conductive layers, mechanical support for the stacked structure, and definition of vertical spacing. The sacrificial layers (119, 129, 139) simultaneously define trench positions, control insulation layer thickness, and serve as etch stop layers. This multi-functionality reduces the need for additional dedicated layers and steps.
Data Source
AI summary
Provided are a nonvolatile memory device and a method for fabricating the same. The method includes sequentially stacking on a semiconductor substrate a first interlayer dielectric film, a first sacrificial layer, a second interlayer dielectric film, and a second sacrificial layer, forming a resistance variable layer and a first electrode penetrating the first and second interlayer dielectric films and the first and second sacrificial layers, forming an upper trench by removing a top portion of the first electrode, filling the upper trench with a channel layer, exposing a portion of a side surface of the resistance variable layer by removing the second sacrificial layer, forming an insulation layer within the channel layer, and forming a second electrode on the exposed resistance variable layer.