3D Cross-Point NVM Layout With Split Bit Lines for Higher Cell Density
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Solution Overview
Problem
Conventional 3D cross-point ReRAM architectures face integration issues and cell density penalties, limiting the performance of non-volatile memory (NVM) in neuromorphic computing applications.
Innovation Solution
A 3D cross-point NVM architecture is developed with vertically stacked word lines running parallel to the substrate and bit lines perpendicular to them, utilizing a patterned dielectric material stack with alternating first and recessed second dielectric material layers, and a dielectric switching material layer between each word line-bit line combination, enhancing cell density and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D cross-point ReRAM architecture is used, then memory capacity is achieved, but cell density is limited due to integration issues
Solution Approach 1:
The patent segments the bit line structure into two distinct parts: first bit lines located within the dielectric material stack and second bit lines located in the interlayer dielectric material layer. This segmentation allows each bit line type to be independently formed and optimized, resolving integration issues while maximizing cell density in the cross-point memory architecture
Solution Approach 2:
The patent transitions from a conventional single-layer bit line structure to a two-layer bit line structure by placing first bit lines in the dielectric material stack and second bit lines in the interlayer dielectric material layer. This dimensional change enables doubled cell density while maintaining manufacturability through separate formation processes for each bit line type
2Quantity of substance
If vertically stacked word lines are implemented, then memory capacity increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the bit line formation into two separate manufacturing steps: forming first bit lines in the dielectric material stack followed by forming second bit lines in the interlayer dielectric material layer. This segmentation simplifies the overall manufacturing process by allowing each bit line type to be formed using standard semiconductor fabrication techniques independently, rather than requiring complex single-step processes
Solution Approach 2:
The patent performs preliminary action by forming the first bit lines within the dielectric material stack before forming the second bit lines in the interlayer dielectric material layer. This sequential approach prepares the structure in advance, allowing subsequent processing steps to build upon the established first bit lines without requiring rework or complex integration
Data Source
AI summary
A non-volatile memory having a 3D cross-point architecture and twice the cell density is provided in which vertically stacked word lines run in plane (i.e., parallel) to the substrate and bit lines runs perpendicular to the vertically stacked word lines. The vertically stacked word lines are located in a patterned dielectric material stack that includes alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layers vertically separate each word line within each vertical stack of word lines and the recessed second dielectric material layers are located laterally adjacent to the word lines. A dielectric switching material layer is located between each word line-bit line combination. Some of the bit lines are located in the dielectric material stack and some of the bit lines are located in an interlayer dielectric material layer.