3D Non-Volatile Memory Stack Structure for Electrical Isolation
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Solution Overview
Problem
Current non-volatile memory devices face limitations in integration and efficiency due to electrical interference between neighboring memory cells, leading to restricted capacity and speed, and challenges in reducing interference.
Innovation Solution
A non-volatile memory device with a multi-layer stack structure incorporating first and second semiconductor layers, control gate electrodes, body contact layers, charge storage layers, tunneling insulation layers, and blocking insulation layers, along with a cell array unit and operating layer selecting unit, which includes a pre-charging unit, layer control unit, and even/odd selecting unit to manage bitlines and improve integration and data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multi-layer stack structure is used to increase integration, then capacity is improved, but electrical interference between neighboring memory cells increases
Solution Approach 1:
The patent transitions from a planar two-dimensional memory structure to a three-dimensional vertical stack structure. Multiple memory cells are stacked vertically along the third dimension, allowing increased integration capacity within the same footprint while using insulation layers to manage electrical interference in this new dimensional arrangement.
Solution Approach 2:
Insulation layers are introduced as intermediary elements between adjacent memory cells and between the control gate electrode and body contact layers. These intermediary insulation layers act as electrical barriers that prevent harmful electrical interference while allowing the multi-layer stack structure to maintain its high integration capacity.
2Ease of manufacture
If planar-type non-volatile memory devices are used, then manufacturing is simpler, but capacity and speed are limited
Solution Approach 1:
The invention moves from planar two-dimensional cell arrangement to a three-dimensional vertical stack configuration. This dimensional change enables significantly increased storage capacity by stacking multiple memory cells vertically, while the manufacturing process maintains relative simplicity by using standard layer deposition and patterning techniques adapted for vertical structures.
3Quantity of substance
If distances between memory cells are reduced to increase integration, then capacity is improved, but electrical interference between neighboring cells increases
Solution Approach 1:
Instead of reducing horizontal distances between cells in the planar direction, the patent stacks memory cells vertically in the third dimension. This allows high integration density to be achieved without further reducing the already minimal horizontal spacing between neighboring cells.
Solution Approach 2:
Insulation layers are positioned between adjacent memory cells and between conductive elements to provide electrical isolation. These intermediary layers enable cells to be placed at minimal distances while preventing electrical interference, thus achieving high integration density without sacrificing electrical isolation.
Data Source
AI summary
A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.