3D Non-Volatile Memory with Stacked Sense Amplifiers for Parallel Operations
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Solution Overview
Problem
Current memory systems face limitations in performance due to insufficient parallelism during memory operations, which affects the efficiency and speed of writing and reading data in non-volatile memory systems.
Innovation Solution
An integrated memory assembly is introduced, featuring a memory die and a control die bonded together, with a three-dimensional non-volatile memory structure and control circuits on both dies, allowing concurrent memory operations on separate subsets of memory cells, thereby increasing parallelism and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If control circuits are integrated on the same die as the memory array, then device complexity is reduced and integration is improved, but parallelism during memory operations is limited due to shared resources
Solution Approach 1:
The memory array is divided into multiple independent sub-arrays, each with its own dedicated control circuit. This segmentation allows simultaneous operation on multiple sub-arrays, increasing parallelism while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture where memory arrays and control circuits are vertically arranged across multiple dies. This dimensional change enables increased parallelism without proportionally increasing die area complexity.
2Productivity
If control circuits are placed on a separate die from the memory array, then parallelism can be increased through independent operation, but device complexity and inter-die communication overhead increase
Solution Approach 1:
Control circuits for multiple sub-arrays are merged onto a single control die, allowing them to operate in parallel while sharing common control logic and resources. This reduces overall device complexity compared to having separate control circuits for each sub-array.
Solution Approach 2:
A standardized interface layer is introduced between the memory arrays and control circuits, acting as an intermediary that simplifies inter-die communication. This interface layer abstracts the complexity of parallel operations and provides a uniform method for data transfer between dies.
3Productivity
If the memory array is divided into multiple sub-arrays with separate control circuits, then parallelism and performance are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs alignment marks and reference structures that create equipotential alignment zones, ensuring that multiple dies can be precisely aligned during assembly. This reduces the impact of manufacturing variations on the overall system performance.
Solution Approach 2:
The design allows for post-fabrication adjustment of alignment parameters through trimmable resistors and adjustable delay circuits. This capability compensates for manufacturing tolerances and ensures optimal performance despite variations in die alignment.
Data Source
AI summary
An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.