3D Non-Volatile Memory Device Step Height Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of three-dimensional non-volatile memory devices is hindered by step height differences between cell and peripheral circuit regions, leading to difficulties in forming contacts and potential attacks on structures underneath contact holes.
Innovation Solution
A method that involves etching the cell region to a lower height than the peripheral circuit region, forming a control gate structure with alternately stacked inter-layer dielectric layers and control gate electrodes, and using insulation layers to create a flat surface for contact formation, thereby simplifying the process and preventing not-open contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of gate electrode layers and inter-layer dielectric layers is increased to further increase integration degree, then the integration degree is improved, but step height difference between cell regions and peripheral circuit regions increases causing contact formation difficulties
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure by vertically stacking multiple gate electrode layers and inter-layer dielectric layers. This dimensional change allows integration degree to increase without proportionally increasing the lateral footprint, thereby reducing the step height difference between cell and peripheral circuit regions.
Solution Approach 2:
The patent implements a nested structure where multiple gate electrode layers are embedded within alternating inter-layer dielectric layers, creating a compact vertical stack. This nesting approach allows multiple functional layers to occupy the same lateral space, increasing integration while maintaining a controlled overall height profile.
2Quantity of substance
If the number of gate electrode layers and inter-layer dielectric layers is increased to further increase integration degree, then the integration degree is improved, but contact hole aspect ratio increases leading to not-open contacts and attacks on structures underneath
Solution Approach 1:
By stacking gate electrode layers vertically in the third dimension, the patent increases integration degree without requiring deeper contact holes. The vertical stacking distributes the structure's height across multiple layers rather than requiring a single deep structure, thereby maintaining contact hole aspect ratios within acceptable limits and preventing not-open contacts.
Solution Approach 2:
The patent segments the gate electrode structure into multiple discrete layers separated by inter-layer dielectric layers. This segmentation allows each layer to be formed and connected independently through contact holes, reducing the overall aspect ratio requirement for any single contact hole and improving contact formation reliability.
3Quantity of substance
If the number of gate electrode layers and inter-layer dielectric layers is increased to further increase integration degree, then the integration degree is improved, but process complexity increases making contact formation difficult
Solution Approach 1:
The patent merges the formation of multiple gate electrode layers and inter-layer dielectric layers into a single integrated stack structure. This consolidation allows the entire multi-layer assembly to be processed as one unit, simplifying subsequent contact formation steps and reducing overall process complexity despite the increased number of layers.
Solution Approach 2:
The inter-layer dielectric layers serve multiple functions: they provide electrical isolation between gate electrode layers, provide structural support for the stacked configuration, and contribute to the overall planarization of the device surface. This multi-functionality reduces the need for additional specialized layers, simplifying the overall process.
Data Source
AI summary
A non-volatile memory device includes a semiconductor substrate having a peripheral circuit region and a cell region, wherein the cell region of the semiconductor substrate is lower in height than the peripheral circuit region of the semiconductor substrate, a control gate structure disposed over the cell region of the semiconductor substrate and comprising a plurality of inter-layer dielectric layers that are alternately stacked with a plurality of control gate electrodes, a first insulation layer covering the cell region of the semiconductor substrate where the control gate structure is formed, a selection gate electrode disposed over the first insulation layer, and a peripheral circuit device disposed over the peripheral circuit region of the semiconductor substrate.