3D On-Chip Inductor Using Through-Silicon Vias
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Solution Overview
Problem
Conventional inductors in integrated circuit devices consume excessive metal resources, have limited inductance values, and induce unfavorable electromagnetic interference (EMI) due to their two-dimensional geometry and substantial parallel alignment with other trace layers, leading to high chip costs and inefficient use of space.
Innovation Solution
The integration of three-dimensional through-silicon vias (TSVs) that extend from the Front-End-Of-the-Line (FEOL) section into the Redistributed Design Layer (RDL) and Back-End-Of-the-Line (BEOL) section, increasing inductance density by allowing a three-dimensional geometry and minimizing EMI through symmetrical and asymmetric designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional two-dimensional inductors are used in metal layers, then inductors can be fabricated using standard processes, but they consume excessive metal layer resources and do not provide sufficient current capacity or high enough quality factor
Solution Approach 1:
The patent transitions from conventional two-dimensional planar inductor geometries to three-dimensional vertical structures by extending inductor traces through multiple metal layers using through-silicon vias (TSVs). This dimensional change allows the inductor to achieve higher inductance values and current capacity without consuming excessive metal resources in a single layer, as the inductive path is distributed across multiple layers vertically.
2Ease of manufacture
If conventional two-dimensional inductors are used with traces parallel to other trace layers, then fabrication is simplified, but they induce unfavorable electromagnetic interference (EMI) effects on other components
Solution Approach 1:
The patent resolves the EMI issue by moving the inductor structure from a two-dimensional planar configuration where traces are parallel to other layers into a three-dimensional vertical configuration. The through-silicon via connections allow the inductor to extend vertically through multiple metal layers, reducing the parallel alignment with other trace layers and thereby minimizing electromagnetic interference with adjacent components while maintaining compatibility with standard fabrication processes.
3Object-generated harmful factors
If inductor available height in BEOL section away from substrate is reduced to minimize undesired coupling, then EMI is reduced, but inductance density and inductance values are limited
Solution Approach 1:
The patent overcomes the limitation of reduced inductor available height by utilizing the vertical dimension through through-silicon vias. Instead of being constrained to a limited height within a single metal layer, the inductor structure extends vertically through multiple metal layers in the BEOL section, effectively increasing the available inductor path length and achieving higher inductance density without increasing the horizontal footprint or causing excessive coupling with the substrate.
4Quantity of substance
If spiral multi-turn inductor geometry is used to increase inductance value, then inductance density improves, but it requires multiple metal layers and creates overlap regions that cause capacitive coupling
Solution Approach 1:
The patent avoids the complexities of spiral multi-turn geometries by implementing a vertical three-dimensional inductor structure using through-silicon vias connecting linear or simplified trace patterns across multiple metal layers. This approach achieves high inductance values through the vertical extension rather than through complex planar spirals, thereby reducing capacitive coupling between overlapping traces and simplifying the overall device structure while maintaining high inductance density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances inductance density and reduces EMI, enabling higher inductance values in smaller spaces, thus reducing chip costs and improving the efficiency of integrated circuit components.
Implementation Method 1
An on-chip inductor is a passive electrical component that can store energy in a magnetic field created by the current passing through it. The turns concentrate the magnetic field flux induced by current flowing through each turn of the conductor in an 'inductive' area within the inductor turns.
Implementation Method 2
An on-chip inductor is a passive electrical component that can store energy in a magnetic field created by the current passing through it.
Data Source
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AI summary
A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments (704) of a first metal layer, a plurality of segments (706) of a second metal layer, a first inductor input (708) a second inductor input (710) and a plurality of through silicon vias (702) coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip