3D On-Chip Inductor Layout for Compact High-Q Wireless Circuits
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Solution Overview
Problem
Existing electronic devices with wireless communications circuitry face challenges in providing inductors with sufficient performance while minimizing area consumption and optimizing quality factor and self-resonance frequency.
Innovation Solution
The implementation of three-dimensional (3D) on-chip inductors on a semiconductor substrate, featuring a stack of windings in different metallization layers with additional windings laterally surrounding the stack, minimizes area occupation and fringing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional two-dimensional inductors are used, then sufficient inductive performance can be achieved, but excessive chip area is consumed
Solution Approach 1:
The patent transitions from traditional two-dimensional planar inductor layouts to three-dimensional stacked inductor structures. Multiple windings are arranged in different metallization layers (M1, M2, M3) stacked vertically, with additional windings laterally surrounding the stack. This dimensional transformation enables achieving sufficient inductance values while occupying minimal chip area, directly resolving the contradiction between area efficiency and inductive performance.
2Area of moving object
If inductor area is reduced, then chip space is optimized, but quality factor deteriorates
Solution Approach 1:
By stacking windings in multiple metallization layers vertically, the inductor achieves high inductance density without increasing lateral footprint. The three-dimensional configuration maintains adequate winding separation and overlap ratios, preserving quality factor while minimizing inductor area occupation on the chip.
Solution Approach 2:
The patent implements a nested winding structure where additional windings laterally surround the central stacked windings. This nested configuration maximizes the use of available space around the vertical stack, adding inductance contribution without increasing the overall inductor footprint, thus maintaining high quality factor in a compact area.
3Area of moving object
If inductor area is reduced, then chip space is optimized, but self-resonance frequency deteriorates
Solution Approach 1:
The vertical stacking of windings in multiple metallization layers creates a compact three-dimensional structure that reduces parasitic capacitance between windings. The increased vertical separation and optimized lateral spacing in the 3D configuration minimize fringing effects, thereby maintaining high self-resonance frequency while occupying minimal chip area.
Data Source
AI summary
An electronic device may include wireless circuitry. The wireless circuitry may include inductors. The inductors may include an on-chip three-dimensional (3D) inductor. The 3D inductor may include a stack of windings in different metallization layers of the substrate. The 3D inductor may include at least one additional winding formed from at least one of the same metallization layers as the stack of windings. The at least one additional winding may laterally surround at least one of the windings from the stack of windings. The stack of windings may be vertically aligned or staggered. The at least one additional winding may be arranged in a vertically aligned stack or a staggered stack. Two or more stacks of windings may be separated by a winding between the stacks. The inductor may occupy a minimal amount of area while minimizing fringing capacitance, thereby optimizing quality factor and self-resonance frequency.