3D Optoelectronic Module Layout for Light and EMI Immunity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SIPs face conflicting needs of immunity to light and electromagnetic interference (EMI) from light-emitting devices, while maintaining low thermal resistance and short interconnect lengths, which are typically addressed by planar layouts that compromise performance.
Innovation Solution
A 3-dimensional (3D) device arrangement where a driver IC die is stacked with a light-emitting device and optionally a passive device, utilizing a light blocking layer and carrier layers with metal posts to minimize EMI and light interference, and provide low inductance and thermal conductivity paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If devices are arranged in a planar layout side-by-side on PCB, then ease of manufacture is improved, but immunity to light and EMI deteriorates and interconnect length increases
Solution Approach 1:
The patent transitions from a planar 2D layout to a three-dimensional stacked arrangement where the driver IC die is positioned beneath the light-emitting device, vertically integrating components that were previously placed side-by-side on the PCB. This dimensional change enables shorter interconnects and improved immunity to light and EMI while maintaining manufacturability through established flip-chip and stacking technologies.
2Object-affected harmful factors
If devices are stacked in 3D arrangement, then immunity to light and EMI is improved and interconnect length is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the stacked structure: the driver IC die provides both electrical driving functions and serves as a mounting platform for the light-emitting device, while the substrate integrates mechanical support, electrical interconnection, and thermal management functions. This consolidation reduces overall device complexity despite the three-dimensional arrangement by eliminating separate mounting structures and interconnect pathways.
3Length of moving object
If devices are placed close together to minimize interconnect length, then inductance and resistance are reduced, but thermal resistance to ambient increases due to mutual heating
Solution Approach 1:
The patent segments the thermal management function from the electrical interconnection function by implementing dedicated thermal vias and heat dissipation pathways through the substrate that are separate from the electrical signal paths. This allows the driver IC die and light-emitting device to be positioned in close proximity for minimal inductance while maintaining independent thermal evacuation routes to the ambient environment.
4Object-affected harmful factors
If light blocking and EMI shielding are added to protect driver IC, then immunity to light and EMI is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The substrate serves multiple functions simultaneously: it provides mechanical support for stacking, electrical interconnection between devices, thermal management pathways, and inherent EMI shielding through its grounded structure. The driver IC die substrate itself acts as the primary EMI shield, eliminating the need for separate shielding components and reducing overall device complexity while maintaining immunity to light and EMI.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves high immunity to light and EMI, with short interconnect lengths and low thermal resistance, enhancing the performance of SIPs by reducing inductance and resistance.
Implementation Method 1
A light blocking layer is on sidewalls and on a bottom of the substrate... The light blocking layer can block at least 90% of incident light received from light emitter
Implementation Method 2
The first bondable features are flipchip mounted with a solder connection to a first portion of the bond pads
Implementation Method 3
carrier layers region that comprises a dielectric material, with at least one metal post extending through its thickness
Implementation Method 4
The first bondable features are flipchip mounted with a solder connection to a first portion of the bond pads
Data Source
AI summary
A system in a package (SIP) (195) includes carrier layer regions (107) that have a dielectric material with a metal post (109) therethrough, where adjacent carrier layer regions define a gap. A driver IC die (110) is positioned in the gap having nodes connected to bond pads (111) exposed by openings in a top side of a first passivation layer (113), with the bond pads facing up. A dielectric layer (116) is on the first passivation layer and carrier layer region (107) that includes filled through vias (116a) coupled to the bond pads and to the metal post (109). A light blocking layer (118) is on sidewalls and a bottom of the substrate. A first device (140) includes a light emitter that has first bondable features (151a). The light blocking layer blocks at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.