3D OS NAND Memory Architecture Without DRAM Bus Overhead
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing circuit area and power consumption due to the use of separate cache memories and NAND memory devices, which increase circuit area and power consumption through bus line connections.
Innovation Solution
A computer system is designed with a processor and memory that overlap, utilizing transistors with a metal oxide in the channel formation region, and integrates a three-dimensional NAND memory device without a DRAM, enabling direct electrical connections between processor and memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate cache memory and NAND memory device are used with bus line connections, then data processing speed is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent combines the cache memory and NAND memory device into a single integrated structure where the cache is formed directly over the NAND memory device. This merging eliminates the need for separate bus line connections and reduces the overall circuit area while maintaining high data processing speed through direct electrical connection.
Solution Approach 2:
The cache memory is nested directly over the NAND memory device, with the cache occupying the space above the NAND structure. This nested configuration allows both memory types to coexist in a compact arrangement, reducing circuit area while enabling fast data access through direct coupling.
2Speed
If separate cache memory and NAND memory device are used with bus line connections, then data processing speed is improved, but power consumption increases
Solution Approach 1:
By merging the cache and NAND memory device into a single integrated unit with direct electrical connection, the patent eliminates power consumption associated with signal transmission through bus lines. The integrated structure reduces overall power consumption while maintaining high data processing speed.
3Reliability
If DRAM is used for cache memory, then data retention is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent merges DRAM cache with NAND memory device into an integrated structure, allowing the DRAM to provide superior data retention while the NAND provides nonvolatile storage. This combination achieves both data retention reliability and space efficiency through shared physical infrastructure.
Solution Approach 2:
The integrated memory device serves multiple functions: the DRAM portion provides fast, high-retention cache memory, while the NAND portion provides nonvolatile storage. This multi-functional design achieves both data retention and space efficiency in a single device.
4Ease of manufacture
If traditional separate memory architecture is used, then manufacturing simplicity is maintained, but circuit area increases
Solution Approach 1:
The patent combines cache memory and NAND memory device into a single integrated structure that can be manufactured using modified standard processes. The merging is achieved through direct electrical connection and shared substrate, maintaining manufacturing simplicity while reducing circuit area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces circuit area and power consumption while providing a novel computer system with efficient data processing capabilities.
Implementation Method 1
a memory circuit capable of retaining data even when power is off, which takes advantage of a feature of an extremely low off-state current of a transistor including an oxide semiconductor
Data Source
AI summary
A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.