3D Stacked OSFET-Ferroelectric Memory for AI In-Memory Computing

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Solution Overview

Problem

Conventional Von Neumann architecture is limited in handling high computational loads and data-intensive applications, especially in AI computing, due to the gap between CPU computing speed and memory transmission rate, necessitating a more efficient memory technology for AI hardware acceleration and reduced power consumption.

Innovation Solution

A 3D monolithic stacking memory structure incorporating an oxide-semiconductor field effect transistor (OSFET) as a write-in transistor and a ferroelectric metal-insulator-metal (FEMIM) storage capacitor on BEOL metal layers, forming a 2T1C unit cell for enhanced device integration, storage density, and reduced power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional Von Neumann architecture is used, then CPU computing speed can be maintained, but memory transmission rate becomes the bottleneck causing gap between computing and transmission speeds

Engineering Contradiction:

Improvememory transmission rateVSAvoidarchitecture complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D memory architecture to three-dimensional 3D stacking architecture, vertically stacking memory cells, transistors, and interconnect layers to dramatically increase storage density and bandwidth without increasing footprint area, thereby improving memory transmission rate

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested structures where memory cells are stacked vertically within each other, with multiple layers of storage elements integrated along the vertical dimension, enabling higher capacity and faster access by utilizing the third dimension for data organization

Inventive Principle:

Principle #7Nested doll (Nesting)

2Productivity

If device miniaturization is pursued, then integration density increases, but power consumption and heat dissipation become critical challenges

Engineering Contradiction:

Improvedevice integration densityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent changes the physical parameters of the memory structure by transitioning to 3D stacking with vertically oriented transistors and interconnects, reducing the footprint area and enabling higher integration density while managing power through improved spatial efficiency and reduced wire lengths

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

By moving from 2D planar to 3D vertical architecture, the patent achieves higher device integration density within the same footprint, reducing the number of devices per unit area and thereby lowering overall power consumption and heat generation

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If 3D stacking architecture is implemented, then storage density increases, but manufacturing precision requirements become more stringent

Engineering Contradiction:

Improvestorage densityVSAvoidalignment precision

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent divides the memory structure into discrete stacked layers (memory cell layers, transistor layers, interconnect layers) that can be manufactured and aligned separately, with each layer contributing to the overall 3D architecture while maintaining manufacturability through modular construction

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs nested layer structures where each manufacturing layer is precisely aligned with underlying layers, creating a vertically integrated 3D stack that achieves high storage density while managing alignment precision through systematic layer-by-layer fabrication processes

Inventive Principle:

Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The structure achieves increased device and storage density, reduced power consumption, and supports multilevel analog states for AI in-memory computing, facilitating efficient AI computation by directly processing analog data without digital conversion.

Implementation Method 1

ferroelectric metal-insulator-metal (FEMIM) storage capacitor

Methodology Applied

Scientific EffectFerroelectricity:

Implementation Method 2

oxide-semiconductor field effect transistor (OSFET)

Methodology Applied

Scientific EffectField effect:

Data Source

PatentUS12414304B23D monolithic stacking memory structure with oxide-semiconductor field effect transistor and ferroelectric metal-insulator-metal storage capacitor

Publication Date: 2025.09.09 POWERCHIP SEMICON MFG CORP

AI summary

A 3D monolithic stacking memory structure is provided in the present invention, including a semiconductor substrate, a field effect transistor (FET) on the semiconductor substrate, a plurality of back-end metal layers on the FET and the semiconductor substrate, an oxide-semiconductor FET (OSFET) in the back-end metal layers, wherein a drain of the OSFET is connected with a gate of the FET, and a FEMIM storage capacitor formed on the back-end metal layers, wherein a bottom electrode of the FEMIM storage capacitor is connected with the drain of the OSFET and the gate of the FET, and the FET, the OSFET and the FEMIM storage capacitor are stacked in order from bottom to top on the semiconductor substrate.