3D Oxide Semiconductor Channel Structure for Low-Trap Transistors
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Solution Overview
Problem
Existing oxide semiconductor transistor devices suffer from increased resistance and threshold voltage due to carrier traps at the interfaces between the oxide semiconductor channel layer and adjacent oxide dielectric layers, leading to degraded performance over time.
Innovation Solution
A multilayer oxide semiconductor channel layer with varying oxygen concentrations is used, where a second oxide semiconductor layer with a lower oxygen concentration is positioned between first and third oxide semiconductor layers with higher oxygen concentrations, reducing interfacial carrier traps and enhancing low hysteresis characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer oxide semiconductor channel is used, then the device structure is simple, but carrier traps form at the interfaces with oxide dielectric layers causing increased resistance and threshold voltage
Solution Approach 1:
The oxide semiconductor channel layer is divided into multiple sub-layers (first, second, and third oxide semiconductor layers) with different oxygen concentrations. This segmentation allows each layer to serve a specific function: the first and third layers with higher oxygen concentrations reduce interfacial carrier traps, while the second layer with lower oxygen concentration maintains good electrical characteristics, collectively improving device reliability without excessive complexity
Solution Approach 2:
Different regions of the oxide semiconductor channel layer are assigned different oxygen concentrations tailored to their specific locations and functions. The first oxide semiconductor layer near the gate dielectric interface has higher oxygen concentration to reduce interfacial traps, the second layer has lower oxygen concentration for optimal electrical performance, and the third layer has higher oxygen concentration to protect against environmental degradation, creating local quality optimization throughout the channel structure
2Productivity
If the transistor size is reduced to increase areal density, then device density improves, but performance degradation occurs due to increased interface effects
Solution Approach 1:
The invention transitions from a two-dimensional planar transistor structure to a three-dimensional vertical structure with multiple oxide semiconductor layers stacked in the vertical dimension. This allows the channel to extend through multiple layers with different oxygen concentrations, effectively increasing the channel volume and reducing the relative impact of interfacial effects while maintaining a compact footprint for high areal density
Data Source
AI summary
A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.