3D Semiconductor Package Layout With Backside Capacitors
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Solution Overview
Problem
Existing semiconductor package structures face challenges in thermal and power delivery network design, which reduce the reliability of 3D IC package technology.
Innovation Solution
The semiconductor package structure incorporates a multi-terminal multi-capacitor structure, which is electrically coupled to multiple semiconductor dies through a redistribution layer, allowing for reduced space occupation and improved design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitor placement methods are used in 3D IC packages, then capacitor functionality is achieved, but space occupation increases and design flexibility decreases
Solution Approach 1:
The patent transitions capacitor placement from the horizontal plane to the vertical dimension by positioning capacitors on the backside of the substrate beneath semiconductor dies. This dimensional change allows capacitors to be stacked vertically, significantly reducing the horizontal space occupation while maintaining electrical coupling to power networks through via structures.
Solution Approach 2:
The patent implements nesting by placing capacitors underneath the substrate, effectively nesting them within the existing package structure. The capacitors are positioned in the space below the substrate, utilizing otherwise unused volume and allowing multiple capacitors to be arranged in a compact configuration beneath the active components.
2Adaptability or versatility
If more conductive terminals are reserved for interconnection, then design flexibility improves, but space for capacitor placement decreases
Solution Approach 1:
The patent resolves this contradiction by moving capacitor placement to the vertical dimension beneath the substrate. This allows the top surface of the substrate to be fully utilized for conductive terminals and interconnections, while capacitors occupy the substrate space below, effectively decoupling the space requirements for terminals and capacitors.
3Volume of moving object
If 3D IC package technology is used to reduce footprint, then device size decreases, but thermal and power delivery network reliability problems increase
Solution Approach 1:
The patent introduces an intermediary power delivery network structure consisting of redistribution layers and via structures that connect capacitors to semiconductor dies. This intermediary network provides dedicated power and ground pathways, improving power delivery reliability and thermal management in the compact 3D package configuration.
Data Source
AI summary
A semiconductor package structure includes a frontside redistribution layer, a first semiconductor die, a first capacitor, a conductive terminal, and a backside redistribution layer. The first semiconductor die is disposed over the frontside redistribution layer. The first capacitor is disposed over the frontside redistribution layer and electrically coupled to the first semiconductor die. The conductive terminal is disposed below the frontside redistribution layer and electrically coupled to the frontside redistribution layer. The backside redistribution layer is disposed over the first semiconductor die.