3D Semiconductor Package Layout for Shorter Cache Data Paths
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving miniaturization, high performance, and large capacity while maintaining efficient data transfer paths and cache memory utilization.
Innovation Solution
The semiconductor package design includes a base wiring structure with a first and second bridge chip and cache memory chip, where logic semiconductor chips are adjacent to each other, and conductive posts connect these chips to the base wiring structure, allowing for overlapping and electrical connection, thereby shortening data transfer paths and utilizing cache memory chips as L3 cache without increasing horizontal area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If logic semiconductor chips and memory semiconductor structures are arranged in a conventional planar layout, then the package area is reduced, but the data transfer path length increases
Solution Approach 1:
The patent implements a three-dimensional stacked architecture where logic semiconductor chips and memory semiconductor structures are arranged in vertical layers rather than a conventional planar layout. The first bridge chip is positioned above the base wiring structure, and the second bridge chip is positioned above the first bridge chip, creating multiple vertical levels. This dimensional transition from 2D to 3D space allows simultaneous reduction of data transfer path length and maintenance of compact package area.
2Productivity
If cache memory chip is added to increase L3 cache capacity, then the performance is improved, but the horizontal area of the package increases
Solution Approach 1:
The cache memory chip is positioned in the vertical dimension above the base wiring structure, overlapping with the first bridge chip in the horizontal projection. This vertical stacking arrangement allows the cache memory chip to be integrated into the three-dimensional architecture without increasing the horizontal footprint of the package, thereby increasing L3 cache capacity while maintaining compact horizontal area.
Solution Approach 2:
The cache memory chip is nested within the vertical stack of the three-dimensional architecture, positioned between the base wiring structure and the first bridge chip. This nesting arrangement allows multiple functional components to occupy the same horizontal space at different vertical levels, effectively increasing cache capacity without expanding the horizontal package area.
3Reliability
If more bridge chips are added to connect logic chips, then the electrical connectivity is improved, but the device complexity increases
Solution Approach 1:
The patent divides the interconnection function into multiple specialized bridge chips positioned at different vertical levels. The first bridge chip handles connections between the base wiring structure and the logic semiconductor chips, while the second bridge chip handles connections between the first bridge chip and the memory semiconductor structures. This segmentation of connectivity functions into distinct layers improves electrical connectivity efficiency while managing complexity through functional specialization.
Data Source
AI summary
A semiconductor package may include a base wiring structure, a first bridge chip and a cache memory chip on the base wiring structure and spaced apart from each other in a horizontal direction, and logic semiconductor chips adjacent to each other on the first bridge chip and the cache memory chip. Logic semiconductor chips each may include a cache memory. The first bridge chip may overlap at least two of the logic semiconductor chips in a vertical direction and the first bridge chip may include first bridge wirings electrically connecting at least two of the logic semiconductor chips. The cache memory chip may overlap the cache memory of at least one of the logic semiconductor chips in the vertical direction and the cache memory chip may be electrically connected to the cache memory of at least one of the logic semiconductor chips.