3D Semiconductor Package Wiring for Defective Capacitor Isolation
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Solution Overview
Problem
In 3-dimensional integrated circuit chips, defects in the capacitor die lead to the entire chip being deemed defective, resulting in significant losses and increased manufacturing costs due to the discarding of normally operating logic dies.
Innovation Solution
The semiconductor package divides the plane of the capacitor die into regions, each containing a capacitor structure. If a defect is detected, the region with the defective capacitor is isolated using the substrate's wire structure, allowing the chip to function normally by electrically separating the defective capacitor from the logic die and connecting the defect-free capacitor to a through silicon via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 3-dimensional integrated circuit chip is manufactured by bonding a lower capacitor die and an upper logic die, then power integrity characteristics are improved through high-capacity capacitors, but a defect in the capacitor die results in the entire chip being deemed defective, leading to significant losses and reduced yield
Solution Approach 1:
The capacitor die is divided into multiple regions, each containing a capacitor structure. This segmentation allows individual regions to be independently evaluated and isolated, so that a defect in one region does not necessarily render the entire die defective. The logic die can continue to function with defect-free capacitor regions, thereby improving manufacturing yield while maintaining power integrity.
Solution Approach 2:
The patent extracts the defective capacitor region from the functional system by isolating it through wire structures. The defective capacitor structure is electrically separated from the logic die, removing the harmful effect of the defect while preserving the functionality of the logic die and defect-free capacitor regions.
2Reliability
If the entire capacitor die is discarded when a defect is detected, then reliability is maintained by ensuring only defect-free chips are produced, but manufacturing costs increase and yield decreases due to the discarding of normally operating logic dies
Solution Approach 1:
Instead of treating the entire capacitor die uniformly, the patent applies local quality assessment to individual regions. Each region containing a capacitor structure is evaluated separately, and only the defective regions are isolated. This allows the majority of the die with functional capacitors to be utilized, reducing material waste and manufacturing costs while maintaining the reliability of the logic die.
Solution Approach 2:
The patent recovers value from previously defective capacitor dies by isolating and removing only the defective capacitor regions. The logic die and defect-free capacitor regions are recovered and reused, transforming what would have been a complete loss into a partial recovery that maintains product reliability while reducing manufacturing costs.
3Productivity
If the capacitor die plane is divided into multiple regions with individual capacitor structures, then defective regions can be isolated to save functional logic dies, but device complexity increases due to additional wiring and isolation structures
Solution Approach 1:
The capacitor die plane is divided into multiple regions, each containing a capacitor structure. This segmentation enables selective isolation of defective regions through wire structures, allowing functional regions to remain connected to the logic die. The increased complexity is localized to the wiring layer, while the overall device functionality is preserved and manufacturing yield is improved.
Data Source
AI summary
A semiconductor package including: a substrate that includes a wiring line; and a 3-dimensional integrated circuit structure on the substrate, the 3-dimensional integrated circuit structure including a first die and a second die on the first die, the first die including a first capacitor structure having a defect, a second capacitor structure free of defects, and a plurality of through silicon vias connected to the second die, wherein the first capacitor structure is electrically separated from the second die, and the second capacitor structure is electrically connected to a corresponding through silicon via among the plurality of through silicon vias through the wiring line.