3D Semiconductor Package Capacitors for High Capacitance and Low ESR
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing minimum feature sizes, leading to issues in the fabrication processes of semiconductor devices, such as increased complexity and inefficiencies in integrating high-efficiency capacitors with low equivalent series resistance (ESR) in densely packed electronic components.
Innovation Solution
The implementation of vertically stacked integrated passive devices (IPDs), specifically deep trench capacitors (DTCs) and metal-oxide-metal (MOM) or metal-insulator-metal (MIM) capacitors, connected through solder and via connections within semiconductor packages like integrated fan-out (InFO) or chip-on-wafer-on-substrate (CoWoS) structures, to form high-capacitance decoupling capacitors with reduced ESR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional planar capacitor structures are used, then fabrication process is simpler, but capacitance density and ESR performance are insufficient
Solution Approach 1:
The patent transitions from planar (2D) capacitor structures to vertically stacked (3D) configurations. Multiple capacitor layers are stacked in the vertical dimension, achieving higher capacitance density without increasing lateral footprint. This dimensional transition resolves the contradiction by enabling high capacitance density while maintaining manageable fabrication complexity through established thin-film deposition and patterning techniques.
Solution Approach 2:
The patent implements nested capacitor structures where smaller capacitors are positioned within or between larger capacitor structures. This nesting approach maximizes space utilization and achieves high capacitance density in a compact volume, resolving the contradiction between manufacturing simplicity and performance requirements.
2Productivity
If minimum feature size is reduced to increase integration density, then more components fit in given area, but fabrication process complexity and inefficiencies increase
Solution Approach 1:
The patent addresses integration density by utilizing the vertical dimension for capacitor stacking rather than continuously reducing lateral feature sizes. This approach achieves high integration density through 3D packaging and vertical interconnects, avoiding the fabrication complexity and process inefficiencies associated with extreme miniaturization in the lateral direction.
Solution Approach 2:
The patent divides the capacitor structure into multiple discrete layers and segments, each fabricated using standard process steps. This segmentation allows parallel processing and modular fabrication, maintaining productivity and reducing overall process complexity even as integration density increases.
3Reliability
If vertically stacked IPDs are implemented, then capacitance density and ESR performance improve, but device structure becomes more complex
Solution Approach 1:
The patent designs vertically stacked IPD structures that serve multiple functions: decoupling, filtering, and signal integrity enhancement. The same vertical stack configuration provides both high capacitance density and low ESR performance simultaneously, achieving improved reliability without proportionally increasing structural complexity.
Solution Approach 2:
The patent merges multiple capacitor functions into a single vertically integrated structure. By combining multiple capacitor elements in series and parallel configurations within the vertical stack, the design achieves superior ESR and capacitance characteristics while presenting a unified structural solution rather than separate components.
Data Source
AI summary
An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.