3D Semiconductor Package Layout for Chiplet and Communication Chip Integration
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Solution Overview
Problem
The increasing demand for smaller electronic devices with large battery capacity necessitates reducing the space occupied by communication chip packages within semiconductor packages, as dividing application processors into chiplets leads to larger package sizes and requires separate communication chip packages.
Innovation Solution
An application processor is divided into a first and second chiplet, mounted on the lower package of a package-on-package (PoP) device, with a communication chip on the upper package, eliminating the need for a separate communication chip package and allowing efficient heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an application processor is divided into chiplets, then manufacturing cost is reduced and yield is improved, but the space occupied by the semiconductor package becomes larger
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional package-on-package structure. The application processor chiplets are mounted on a lower package substrate, while the communication chip is mounted on an upper package substrate positioned vertically above the lower package. This vertical stacking approach allows multiple functional components to occupy different spatial layers, effectively reducing the overall footprint area while maintaining all necessary functional elements.
Solution Approach 2:
The patent implements a nested configuration where the upper package containing the communication chip is positioned directly above and partially overlaps the lower package containing the application processor chiplets. This nested arrangement allows the communication chip package to utilize the vertical space above the application processor package, thereby consolidating multiple components into a compact integrated structure that minimizes the total occupied area.
2Adaptability or versatility
If a separate communication chip package is used, then communication functionality is provided, but the board size in electronic products increases
Solution Approach 1:
The patent merges the application processor package and the communication chip package into a single integrated package-on-package structure. The lower package substrate and upper package substrate are vertically stacked and mechanically/electrically connected, combining what were previously separate packages into one unified component. This integration eliminates the need for separate mounting of communication chips on the motherboard, thereby reducing the overall board size while maintaining full communication functionality.
Solution Approach 2:
The patent utilizes the vertical dimension to accommodate the communication chip above the application processor chiplets. By positioning the communication chip on the upper package substrate in the vertical direction rather than placing it laterally adjacent to the application processor on the same plane, the design achieves three-dimensional space utilization that significantly reduces the two-dimensional board footprint.
3Ease of manufacture
If chiplets are mounted on the lower package, then manufacturing flexibility is improved, but the package structure becomes more complex
Solution Approach 1:
The patent segments the application processor into multiple independent chiplets (first chiplet, second chiplet, etc.) that are separately manufactured and then mounted on the lower package substrate. This segmentation allows each chiplet to be produced using optimized manufacturing processes for its specific function, improving manufacturing flexibility and yield. The modular nature of chiplets enables independent fabrication, testing, and replacement, simplifying the overall manufacturing ecosystem despite the multi-component structure.
Solution Approach 2:
The lower package substrate serves multiple functions: it provides mechanical support for the chiplets, establishes electrical connections between chiplets and the external environment, and acts as a mounting platform for the upper package substrate. This multi-functional design consolidates several roles into a single component, reducing the overall system complexity while maintaining manufacturing flexibility through standardized package interfaces.
Data Source
AI summary
A semiconductor package includes a first redistribution structure, a first chiplet on the first redistribution structure, a second chiplet on the first redistribution structure and proximate the first chiplet in a horizontal direction parallel to a surface of the first redistribution structure, a second redistribution structure on the first chiplet and on the second chiplet, and a communication chip on the second redistribution structure.