3D Semiconductor Package With Composite Wafer And Through-Package Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces limitations in increasing integration density due to physical constraints in two-dimensional integrated circuit (IC) formation, as further reductions in feature size are hindered by the complexity of designs required for higher device densities.
Innovation Solution
A method involving the formation of a composite wafer with a backside passivation layer, die bonding structures, conductive posts, redistribution lines, and connectors, allowing for the creation of three-dimensional semiconductor devices by flipping and patterning the composite wafer to expose conductive posts for bonding top packages, thereby overcoming the limitations of two-dimensional integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more devices are integrated into one chip to increase integration density, then the quantity of components increases, but design complexity increases and physical limits are reached
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple semiconductor dies. This dimensional change allows continued increase in integration density without proportionally increasing the complexity of individual die designs, as components are distributed across multiple stacked layers rather than crowded into a single plane.
Solution Approach 2:
The patent divides a single large-scale integration challenge into multiple smaller dies that can be manufactured and tested separately, then stacked together. Each die can be optimized independently, reducing the complexity of design and manufacturing while achieving higher overall integration density through the stacked configuration.
2Quantity of substance
If feature size is reduced to increase integration density, then more components fit in given area, but minimum size limits are approached
Solution Approach 1:
Instead of continuing to reduce feature sizes in two dimensions, the patent exploits the third dimension (vertical stacking) to achieve higher integration density. This allows maintaining larger, more manufacturable feature sizes on each die while still increasing overall component quantity through multiple stacked layers.
Solution Approach 2:
The patent implements a nested structure where multiple complete functional dies are stacked one inside another vertically. Each die maintains its own feature size requirements, and the nesting of multiple dies in the vertical dimension achieves higher integration density without further reducing the minimum feature size of individual components.
3Quantity of substance
If multiple dies are stacked to increase integration density, then quantity of components increases, but warpage in package structure increases
Solution Approach 1:
The patent uses a composite wafer structure combining different materials (such as carrier wafer, die attach materials, and buffer layers) to compensate for thermal expansion differences and mechanical stress. This composite construction reduces warpage in the stacked die package while maintaining high integration density.
Solution Approach 2:
The patent introduces intermediary layers (such as die attach adhesives, underfills, and buffer layers) between stacked dies to mechanically couple them and compensate for dimensional mismatches. These intermediary materials act as mediators that reduce stress and prevent warpage while enabling the stacked configuration for higher integration density.
Data Source
AI summary
Embodiments of the present disclosure include a semiconductor device, a package, and methods of forming a semiconductor device and a package. An embodiment is a method including placing a plurality of dies over a passivation layer, the plurality of dies comprising at least one active device, molding the plurality of dies with a first molding material, and forming a plurality of through-package vias (TPVs) in the first molding material, first surfaces of the plurality of TPVs being substantially coplanar with a backside surfaces of the plurality of dies. The method further includes patterning the passivation layer to expose a portion of the first surfaces of the plurality of TPVs, and bonding a plurality of top packages to the first surfaces of the plurality of TPVs.