3D Semiconductor Package Layout With Connect Die Interconnects
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Solution Overview
Problem
Conventional semiconductor packages face issues of high cost, decreased reliability, and large package sizes, leading to suboptimal performance.
Innovation Solution
A method of manufacturing semiconductor devices involving the use of connect dies with interconnects and redistribution structures, coupled with alignment pads and encapsulants, to create a compact and reliable electronic package that electrically connects multiple components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages are used, then manufacturing is simpler, but cost is high and reliability is decreased
Solution Approach 1:
The package structure is divided into multiple functional layers including substrate, encapsulant, interconnect structures, and device components. This segmentation allows each layer to be optimized independently for its specific function, improving overall reliability while managing complexity through modular design
Solution Approach 2:
The patent employs nested structures where interconnect structures are embedded within encapsulant material, which is in turn encapsulated within the substrate housing. This nesting approach consolidates multiple components into a compact hierarchical arrangement, enhancing reliability through integrated design
2Volume of moving object
If conventional semiconductor packages are used, then manufacturing process is traditional, but package size is large
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional vertical stacking, with interconnect structures extending through multiple layers of encapsulant and substrate. This dimensional change dramatically reduces the footprint area while maintaining functional connectivity, achieving compact packaging without oversimplifying manufacturing
Solution Approach 2:
Encapsulant material serves as an intermediary that both electrically isolates and mechanically supports the interconnect structures. This mediator enables compact 3D routing while providing a standardized manufacturing interface, balancing size reduction with manufacturing feasibility
3Speed
If conventional packages are used, then design is simple, but signal path length is long reducing performance
Solution Approach 1:
Signal paths are routed through the vertical dimension using multi-layer interconnect structures embedded in encapsulant, rather than traveling across large planar distances. This 3D routing dramatically shortens signal path lengths, improving transmission speed while the systematic layering manages the inherent structural complexity
4Ease of manufacture
If conventional semiconductor packages are used, then manufacturing is traditional, but cost is excessive
Solution Approach 1:
Multiple functional elements are merged into integrated structures: interconnect structures serve both electrical and mechanical functions, encapsulant provides both insulation and structural support, and substrate housing combines protection with thermal management. This merging reduces the total quantity of separate materials needed while maintaining manufacturability through consolidated processing steps
Data Source
AI summary
In one example, an electronic device includes a lower substrate comprising a lower substrate upper side and a lower substrate lower side, and an upper substrate comprising an upper substrate upper side and an upper substrate lower side. The electronic device also includes a first electronic component and a second electronic component coupled to the upper substrate upper side. A first device interconnect and a second device interconnect couple the lower substrate upper side to the upper substrate lower side. The electronic device also includes a connect die coupled to the lower substrate upper side that electrically couples the first electronic component to the second electronic component. Other examples and related methods are also disclosed herein.